【作者】 雷绍充； 梁峰； 张路文； 王震； 刘泽叶；

【Author】 LEI Shaochong,LIANG Feng,ZHANG Luwen,WANG Zhen, LIU Zeye (School of Electronics and Information,Xi’an Jiaotong University,Xi’an,710049,China)

【机构】 西安交通大学电子与信息工程学院；

【摘要】 未来的纳米电路测试需要更先进的测试压缩技术,本文探讨一种采用多维相似性测试图形的压缩方法。先提出两个种子向量的多维线性解压方法,以构成多维相似性测试图形;再研究多维相似性测试图形序列的约束条件,以构成最大长度序列;然后研究种子向量的压缩方法,以进一步提高测试压缩率;最后通过实验验证多维相似性测试图形的高压缩率与低测试功耗的特征。对五个最大的ISCAS’89电路实验结果表明,本文方法的压缩率都在80倍以上。更多还原

【Abstract】 Future’s nanometer circuit testing will require further advances in test compression technology.This paper provides a solution utilizing multi-dimension similarity test patterns.Firstly, it develops a method to expand two seeds linearly in multi dimensions,and generates test vectors with similarity.Then, preconditions for the test pattern sequence are drawn to construct a maximal length sequence.Thirdly,it studies the method to compress seeds to enhance compression ratio further.Finally, experiments on ISCAS benchmarks are conducted to verify favorable features of high compression ratio and low test power of the generated test patterns.Simulation results demonstrate that the proposed method can achieve compression ratios higher than 80 for the five largest ISCAS’89 benchmarks.更多还原