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一种高速、高精度全差分采样保持电路的ASIC设计

An ASIC Design of a High Speed, High Accuracy Sample-and-hold Circuit

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【作者】 魏微陆卫国郭海东王铮赵京伟

【Author】 WEI Wei1, LU Wei-guo1, Guo Hai-dong2, WANG Zheng1, ZHAO Jing-wei1 1 Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049 2 OmniVision Technologies, Inc. Santa Clara, USA, 95054

【机构】 中国科学院高能物理研究所OmniVision Technologies,Inc.Santa Clara

【摘要】 为了实现新型密集型阵列探测器信号的高速、高密度读出,必须采用专用集成电路技术,利用模数变换器将物理量变换为数字信号后进行串行输出。采样保持电路是模数变换器中的关键单元,决定了整个模数变换过程的性能。本文在国内高能物理领域,首次利用专用集成电路技术,设计实现了一种用于10位、3.3Ms/s采样率的逐次逼近ADC的全差分采样保持电路并成功流片。实测结果表明,本设计达到了预期的设计指标,实现了较高的性能。

【Abstract】 To fulfill the requirement of the high speed and high density readout of modern pixel and segmented detectors, application-specific integrated circuits (ASICs) become the necessities. With the further help of A/D convertors (ADC), physical events are finally translated into digital signals, so that serial outputs can enhance the speed and density of readout. Among all the modules in an ADC, sample-and-hold circuit (S/H) is the crucial one which dominates the overall performance of A/D conversion. This work introduces a fully differential S/H circuit, which, for the first time in domestic high energy physics field, is realized in the form of ASIC. Through a successful tape-out, the design achieved a specification for a successive-approximation ADC of 10 bits and 3.3 Ms/s sampling rate. The measurement results show that, the real chip fully satisfies the preset targets and shows a high performance.

  • 【会议录名称】 第十五届全国核电子学与核探测技术学术年会论文集
  • 【会议名称】第十五届全国核电子学与核探测技术学术年会
  • 【会议时间】2010-08-13
  • 【会议地点】中国贵州贵阳
  • 【分类号】TN492;TL82
  • 【主办单位】中国电子学会核电子学与核探测技术分会、中国核学会核电子学与核探测技术分会
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