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铁电薄膜场效应晶体管存储器件的失效机制及器件力学

The failure mechanism and device mechanics of ferroelectric thin film field-effect transistor memory

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【作者】 周益春杨锋孙静张军

【Author】 ZHOU Yi-chun, YANG Feng, SUN Jing, ZHANG Jun (Key Laboratory of Low Dimensional Materials and Application Technology of the Ministry of Education, Xiangtan University, Xiangtan 411105, China)

【机构】 湘潭大学低维材料及其应用技术教育部重点实验室

【摘要】 基于偶极子翻转理论,通过对薄膜中偶极子的统计分布函数进行积分的方法,改进经典的Preisa-ch模型。由于改进的模型具有历史电场效应,可以用较少的参数方便、准确地仿真薄膜的电滞回线。结合金属-氧化物-半导体(MOS)结构的半导体物理理论,建立了一种描述金属-铁电层-绝缘层-半导体(MFIS)结构电学性能的方程。以Pt/SrBi2Ta2O9(SBT)/ZrO2/Si和Pt/Bi3.25La0.75Ti3O12(BLT)/MgO/Si两种结构为例,模拟了不同的铁电层厚度和绝缘层厚度对两种结构电容-电压(C-V)特性和记忆窗口的影响。模拟结果和实验结果能够较好的符合,从而表明改进的模型能够较好地模拟MFIS结构的C-V特性和记忆窗口。发展了金属-铁电-绝缘体-半导体场效应晶体管(MFIS-FET)模型,并用来研究铁电-电极界面效应。通过假设界面层具有二级介电/铁电相,模拟了铁电晶体管的C-V,I-V和半导体的表面势。模拟的结果显示,当界面层厚度增加时,MFIS-FET的电性能会变坏,说明界面层厚度起了重要的作用。

【Abstract】 Based on the Dipole Swithing theory, the Preisach model was improved through an approximate integral of the statistic distribution function of the dipoles in thin film. The model can predict asymmetric hysteresis loop measured under unconventional situation due to its history-dependent electric field effect. It is recognized that the conventional model for metal-ferroelectric-insulator-silicon (MFIS) capacitor is always not consistent with the experimental observation very well due to negligence of the history-dependent electric field effect. In this letter, combining the switching physics of ferroelectric with silicon physics, an improved model is proposed to investigate the capacitance-voltage (C-V) characteristic and memory window. For two MFIS capacitors with SrBi2Ta2O9 and Bi3.25La0.75Ti3O12 ferroelectric layers, C-V characteristic and memory window were evaluated, and the results are more consistent with the previous experiments than that of the Lue model. An improved metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) model is developed to study the effect of the ferroelectric-electrode interface. By assuming the interface layer posses a secondary dielectric/ferroelectric phase, the C-V, I-V of the ferroelectric transistor and the surface potential of the semiconductor are simulated. The modeling results show that the electric characteristics of MFIS-FET become worse as the interface layer thickness increases, inferring the significant role the thickness plays in the model.

【基金】 教育部科技创新工程重大项目培育资金项目(076044)
  • 【会议录名称】 2009中国功能材料科技与产业高层论坛论文集
  • 【会议名称】2009中国功能材料科技与产业高层论坛
  • 【会议时间】2009-11-07
  • 【会议地点】中国江苏镇江
  • 【分类号】O484
  • 【主办单位】中国仪表功能材料学会、江苏大学、《功能材料》期刊、《功能材料信息》期刊
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