【作者】 高腾飞； 钟洪声；

【Author】 Gao Tengfei Zhong Hongsheng (School of E.E., University of Electronic Science and Technology of China, Chengdu, Sichuan 610054)

【机构】 电子科技大学电子工程学院；

【摘要】 基于0.35umSiGe工艺,本文设计了一款UART的专用芯片。电路采用半定制设计方法,设计流程包括综合、布局布线、静态时序分析和版图后仿真。采用物理综合解决了深亚微米工艺条件下综合库中线负载模型精确度降低的问题。芯片的最长路径时延为8.4ns,平均功耗(50MHz)约为7mW,芯片核心面积为0.18mm2,可以作为硬IP核直接应用于微处理器芯片接口的设计上。更多还原

【Abstract】 This paper presents the ASIC implementation of UART using a 0.35um SiGe process. Semi-custom design method is used and the design flow includes synthesis, place & route, static timing analysis and post-layout simulation. Physical synthesis methodology is used to solve the problem that the precision of wire-load models will be decreased as the ASIC designs move into the deep-submicrometer process era. The delay analysis for critical path is 8.4ns, the average power consumption is about 7mW at a frequency of 50 MHz and the area of the core is about 0.18mm2. It can be used as a hard IP core for the microprocessor interface.更多还原