【作者】 周灵军； 赵宏宇； 徐勋光； 范平志；

【Author】 Linjun Zhou, Hongyu Zhao , Xunguang Xu, Pingzhi Fan Key Lab of Mobile Communications, Southwest Jiaotong University

【机构】 西南交通大学移动通信研究所；

【摘要】 Turbo码因其优异的纠错性能而受到广泛的关注。在实际应用中,在保证译码性能的前提下,还必需解决Turbo码译码时延长和运算复杂度高的问题。本文研究并实现了一种基于纯整数运算的Turbo译码算法的FPGA实现方案。通过采用流水线技术和模块复用等优化设计,可以大大提高译码速度,减少资源消耗。整个设计用Verilog HDL语言描述,在Altera的StmtixⅡ系列上实现,在时钟频率为25MHz,迭代次数为5次时,译码器吞吐量达到1．24Mb／s。更多还原

【Abstract】 Turbo codes which have shown BER performance approaching the Shannon limit have received considerable attention. To successfully apply turbo codes to practical communication systems, one has to overcome the high computation complexity and large decoding delay problems. In this paper we investigate and implement an FPGA architecture based on pure integer Log-MAP algorithm. The design uses pipe-line and module reused technology, thus speeding up the decoding process and reducing the resource consumption significantly. The design is described with Verilog HDL and implemented successfully on the Stratix II series of Altera. A throughput of 1.25Mb/s at 25MHz is achieved with 5 iterations.更多还原