【作者】 徐勇军； 陈治国； 骆祖莹； 李晓维；

【Author】 XU Yong-Jun, CHEN Zhi-Guo, LUO Zu-Ying, LI Xiao-Wei Network Lab, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; School of Physical Electronic, University of Electronic Science and Technology, Chengdu 610054; Department of Computer Science and Technology, TsingHua University, Beijing 100084

【机构】 中国科学院计算技术研究所信息网络室； 清华大学计算机科学与技术系；

【摘要】 随着工艺的发展,功耗成为大规模集成电路设计领域中一个关键性问题。降低电源电压是减少电路动态功耗的一种十分有效的方法,但为了保证系统性能,必须相应地降低电路器件的阈值电压,而这样叉将导致静态功耗呈指数形式增长,进入深亚微米工艺后, 漏电功耗已经能和动态功耗相抗衡,因此,漏屯功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫。诸如HSPICE的精确模拟器可以准确估计漏电功耗,但仅仅适合于小规模电路。本文首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应,然后提出了快速模拟器的漏电模型,最后通过对ISCAS85&89基准电路的实验说明了在精度许可(误差不超过3％) 的前提下,本文的模拟器获得了成百倍的加速,对机器内存的需求量也获得很大降低。更多还原

【Abstract】 As technology scales, power dissipation becomes a critical issue of VLSI circuit design. Lowering power supply voltage is an efficient method to reduce dynamic power. In order to maintain performance, the threshold voltage of device should be reduced accordingly, which results in exponential increase of static power. When deep into deep sub-micro (DSM) process era, leakage power becomes comparable with dynamic power consumption. Fast simulators are urgently needed as well as low leakage design technologies. Precise circuit simulators (such as HSPICE) can accurately account for leakage power estimation, but are only practical for small circuits. Firstly, in this paper, we demonstrate the stack effect of CMOS transistors and primitive logic gates, based on which we bring forward our leakage model of our simulator. And then, we give our experiments on ISCAS85&89 benchmark circuits to show this simulator is hundredfold accelerated compared with HSPICE with endurable accuracy (error under 3%), but the memory requirement is significantly reduced.更多还原