【作者】 朱敏；

【导师】 肖昊；

【作者基本信息】 合肥工业大学 ， 集成电路与系统， 2024， 硕士

【摘要】 后量子密码拥有对抗量子攻击的特性,其中基于格的算法在安全性、密钥大小及计算速度上都能实现很好的平衡,其应用范围广且容易在硬件上实现,在学术和工业领域都受到广泛关注。本文以基于格的数学难题构建的CRYSTALS-Dilithium数字签名算法为研究课题,围绕性能与资源平衡、灵活可配置等设计目标,在对算法的核心算子多项式乘法进行电路优化的基础上,提出一种可重构的CRYSTALS-Dilithium数字签名方案处理器硬件架构。其安全参数可根据需求进行灵活配置,运算流程可根据需要选择。全文主要包括以下研究工作:首先,针对CRYSTALS-Dilithium数字签名算法在不同场景下的应用需求,提出了一种紧凑且高性能的硬件加速处理器,该处理器可支持所有安全级别。具体而言,在签名过程中,首先对三个运算阶段进行状态划分,在不同状态下将多项式系数生成和相关计算的过程并行处理,减少中间结果的存储需求,该方法隐藏部分模块运算所需时间,从而降低运算过程中的延迟。其次,针对可加速多项式乘计算的NTT算法中硬件计算资源和数据位宽的不匹配问题,提出一种基于硬件计算资源融合的位宽收缩乘法设计方案,可避免计算资源的大量空置。具体来说,根据硬件资源处理数据时的固定位宽对数据进行合理划分,确保大部分数据能够直接利用硬件资源进行计算,对于超出范围的部分数据,其运算操作通过按比特位划分,并采用加法和移位等简单运算来代替,这种融合硬件资源的方法支持各种多位宽数据运算。最后,针对取模过程中额外的乘法操作,结合固定模数的特性,提出一种基于快速查找表和K-RED算法的面积高效模乘器电路架构。在取模过程中,该架构通过查找表进行数据压缩,并仅通过加法和移位操作即可完成复杂的取模运算,从而有效降低取模过程的硬件资源开销。实验结果表明,在Xilinx Zynq-7000 FPGA上综合实现的CRYSTALS-Dilithium数字签名硬件加速器的最高运行频率可达170MHz。与Dilithium相关研究相比,提出的设计使用1.4×/1.4×/3.0×/2.2×更少的LUT/FFs/BRAM/DSP,在签名算法中的执行时间上提升近2.8倍。本文提出的紧凑架构使得Dilithium在资源受限设备上的加速成为可能,同时为算法评估提供了参考价值。更多还原

【Abstract】 Post quantum cryptography has the characteristic of resisting quantum attacks,among which lattice based algorithms can achieve a good balance in security,key size,and computing speed.Its application range is wide and easy to implement on hardware,and it has received widespread attention in both academic and industrial fields.This article focuses on the research topic of the CRYSTALS-Dilithium digital signature algorithm based on lattice mathematical problems.Focusing on design goals such as performance and resource balance,flexibility and configurability,a reconfigurable CRYSTALS-Dilithium digital signature scheme processor hardware architecture is proposed based on circuit optimization of the algorithm’s core operator polynomial multiplication.Its safety parameters can be flexibly configured according to needs,and the calculation process can be selected according to needs.The full text mainly includes the following research work:Firstly,a compact and high-performance hardware accelerated processor is proposed to meet the application requirements of the CRYSTALS-Dilithium digital signature algorithm in different scenarios,which can support all security levels.Specifically,during the signature process,the three operation stages are first divided into states,and then the polynomial coefficient generation and related calculations are processed in parallel under different states to optimize the data scheduling mechanism.This method hides the time required for certain module operations,thereby reducing the delay in the operation process.Secondly,a bit width contraction multiplication design scheme based on hardware computing resource fusion is proposed to address the mismatch between hardware computing resources and data bit widths in the NTT algorithm that can accelerate polynomial multiplication computation,which can avoid a large amount of idle computing resources.Specifically,data is reasonably divided based on the fixed bit width of hardware resources when processing data,ensuring that most of the data can be directly calculated using hardware resources.For data that exceeds the range,the operation is divided by bit and replaced by simple operations such as addition and shift.This method of integrating hardware resources supports various multi bit width data operations.Finally,a high-efficiency area multiplier circuit architecture based on fast lookup table and K-RED algorithm is proposed to address the additional multiplication operations during the modulus extraction process,combined with the characteristics of fixed modulus.During the module extraction process,this architecture compresses data through lookup tables and completes complex module extraction operations only through addition and shift operations,effectively reducing the hardware resource overhead of the module extraction process.The experimental results show that the maximum operating frequency of the CRYSTALS-Dilithium digital signature hardware accelerator implemented on Xilinx Zynq-7000 FPGA can reach 170MHz.Compared with the research related to Dilithium,the proposed design uses 1.4×/1.4×/3.0×/2.2×fewer LUT/FFs/BRAM/DSP,which improves the execution time in the signature algorithm by nearly 2.8 times.The compact architecture proposed in this article makes it possible for Dilitium to accelerate on resource limited devices,while providing reference value for algorithm evaluation.更多还原