【作者】 王强；

【导师】 许高斌；

【作者基本信息】 合肥工业大学 ， 集成电路工程（专业学位）， 2024， 硕士

【摘要】 随着互联网时代的到来,数字化和信息化社会进程不断推进,各种带有存储功能的电子设备早已被广泛使用,因此各种存储器如静态随机存储器(Static Random Access Memory,SRAM)、动态随机存取存储器(Dynamic Random Access Memory,DRAM)、闪存(Flash)等的可靠性便显得非常重要。而在所有不同种类的存储器中,DRAM占有了很大的市场份额,应用非常之广泛,所以DRAM的可靠性对于不断发展的信息化社会而言非常重要。但是随着DRAM的不断更新迭代,如从第1代双倍速(1st Generation of Double Data Rate,DDR1)存储器至第5代双倍速(5th Generation of Double Data Rate,DDR5)存储器,DRAM的存储密度不断地增大,而制程工艺尺寸不断缩小,同时其应用的场合越来越多,这也使得DRAM越来越容易受到外界环境干扰而出现数据出错的现象,所以对应用于DRAM的纠错机制的研究便显得尤为重要。因此,本文对DRAM中常用的纠错机制即错误纠正码(Error Correction Code,ECC)技术进行了研究。具体而言,本文的主要工作如下:(1)对DRAM的内部结构特点进行了分析,并以此理解了DDR5储存器设计规范JESD79-5C-v1.30中对于片上(On-die)ECC的规定,然后在此基础之上对目前存储器中广泛使用的单错校正(Single Error Correction,SEC)码即汉明码进行了研究,并指出了将汉明码用作DRAM纠错码的不足之处。依据汉明码的这些缺点,本文通过结合线性分组码的编译码原理以及DRAM的内部结构特点设计了一种新的SEC码,得到了此纠错码的校验矩阵,然后使用Python编程检验了所得校验矩阵的正确性。(2)依据所得纠错码的编译码机制搭建了ECC电路;编码模块的搭建利用了所得SEC码的校验矩阵中校验位与信息位的对应关系,由于本文SEC码为系统码,所以信息位和编码所得校验位是分开的;译码模块则是依据所得纠错码的并行译码机制来搭建的,这种并行译码的机制主要体现在校正子译码即8位校正子分为前5位和后3位并行译码;同时由于此128比特数据的SEC码的编码模块较大,便在译码过程中对编码模块进行了复用,从而简化了整个ECC电路;随后本文依照同样的整体架构对汉明码进行了ECC电路搭建。(3)针对所设计的两种ECC电路,本文使用System Verilog搭建了验证平台,并依据所需要验证的功能点对所搭建的电路进行了验证,然后又对电路进行了实际应用测试。结果表明,依据两种纠错码搭建的ECC电路都可以对128位数据进行单误差纠正,但只有本文SEC码的ECC电路能够不对出现在同一字节中任意位置的两比特错进行误纠而引入误更正,降低了On-die ECC后面的内存列级(rank-level)ECC的风险。随后本文对两种纠错码电路的一些参数进行了比较。更多还原

【Abstract】 With the advent of the Internet era and the continuous advancement of digitalization and information society,various electronic devices with storage functions have long been widely used,so the reliability of various memories such as static random access memory,dynamic random access memory(DRAM),Flash and so on is very important.DRAM has a large market share and is widely used in all different types of memory,so the reliability of DRAM is very important for the ever-evolving information society.However,with the continuous update and iteration of DRAM,such as from the 1st generation of double data rate(DDR1)memory to the 5th generation of double data rate(DDR5)memory,the storage density of DRAM continues to increase,while the size of the manufacturing process continues to shrink,and its application occasions are increasing.This also makes DRAM more and more susceptible to data errors due to external environmental interference,so it is particularly important to study the error correction mechanism applied to DRAM.Therefore,this paper studies the error correction code(ECC)technology,which is commonly used in DRAM.Specifically,the main work of this paper is as follows:(1)The internal structure characteristics of DRAM are analyzed,and the provisions of on-die ECC in DDR5 memory design specification JESD79-5C-v1.30 are understood,and then the single error correction (SEC)code,which is widely used in memory,is studied,and the shortcomings of using Hamming code as DRAM error correction code are pointed out.According to these shortcomings of Hamming code,a new SEC code is designed by combining the decoding principle of linear block code and the internal structure characteristics of DRAM,and the check matrix of the error correction code is obtained,and then the correctness of the obtained check matrix is verified by Python programming.(2)An ECC circuit is built according to the codec mechanism of the obtained error-correcting code.The construction of the coding module makes use of the correspondence between the check bit and the information bit in the check matrix of the obtained SEC code,because the SEC code in this paper is a system code,the information bit and the encoded check bit are separated.The decoding module is built according to the parallel decoding mechanism of the obtained error correction code,which is mainly embodied in the corrector decoding,that is,the 8-bit corrector is divided into the first 5 bits and the last 3 digits in parallel decoding.At the same time,because the encoding module of the SEC code of the 128-bit data is large,the encoding module is reused in the decoding process,so that the whole ECC circuit is simplified.Subsequently,this paper builds the ECC circuit of Hamming code according to the same overall architecture.(3)For the two ECC circuits designed,this paper uses System Verilog to build a verification platform,and verifies the built circuits according to the function points that need to be verified,and then conducts practical application tests on the circuits.The results show that the ECC circuit built based on the two error correction codes can correct the single error of 128-bit data,but only the ECC circuit of the SEC code in this paper don’t introduce false correction because it don’t mis-correct the two-bit error that occurs anywhere in the same byte,which reduces the risk of on-die rank-level ECC behind the on-chip ECC.Subsequently,some parameters of the two types of error correction code circuits are compared.更多还原