【作者】 张宇；

【导师】 陈凯；

【作者基本信息】 电子科技大学 ， 电子信息（专业学位）， 2025， 硕士

【摘要】 功率分析仪可对电压电流进行多种运算分析,而高端功率仪的通道数和各通道需计算的功率参数较多,且需对信号进行高精度谐波分析,其中如何平衡逻辑资源和处理效率,以及在此过程中产生的数据存储问题,均增大了其设计复杂度。本文从FPGA角度,针对功率分析仪提出了全新的数据处理与存储方案,包含高速接口数据接收、上位机通信交互、功率参数计算、DDR存储及其AXI接口读写方案,以及高精度谐波分析等。主要研究内容如下:第一,顶层架构设计上,基于AXI总线互联、XDMA和MIG三大IP核,结合更新时间概念,设计实现一种全新的适用于多通道功率分析仪的数据传输、接收、计算、存储和软硬件交互的架构,将数据处理与存储分成了基于更新时间的实时计算通路和基于DDR深存储的谐波分析通路。并将功率参数计算和谐波分析处理等任务进行合理软硬件划分和存储规划,以在满足实时性要求的同时,降低设计复杂度,更易于调试、维护和功能升级。第二,在基于更新时间的实时计算通路上,除其本身架构设计外,对于多通道功率参数计算功能,还设计实现了一种多卡多同步源的串-并结合功率参数实时计算架构。在该架构下,功率分析仪能通过多个RAM缓存和乒乓读写的方式复用同一套并行计算核,从而大大降低FPGA逻辑资源消耗,其中LUT使用量仅为原来的16.83%;触发器仅为原来的18.514%;DSP则仅为原来的13.03%。第三,在基于DDR深存储的谐波分析通路上,除其本身架构设计外,还在DDR存储的同步采集方法的基础上,根据多通道数据在DDR中的不同存储方式,分别探讨设计了基于线性插值非整数倍率降采样的单点串行架构和N点并行架构。其中N点并行架构是一个通用化设计,可将抽点效率提升为原来的N倍,同时还有效提高了DDR带宽利用率。本文设计的功率分析计算系统已在Xilinx型号为xc7vx485tffg1157-1的FPGA上成功运行,且已在多通道功率分析仪实际项目平台通过了第三方测试验证。更多还原

【Abstract】 The power analyzer can perform various computational analyses on voltage and current.However,high-end power analyzers feature multiple channels,each requiring the calculation of numerous power parameters,as well as high-precision harmonic analysis of signals.Balancing logic resources and processing efficiency,along with the data storage issues arising during the process,significantly increases design complexity.This thesis proposes a novel data processing and storage solution for power analyzers from an FPGA perspective,encompassing high-speed interface data reception,host computer communication,power parameter calculation,DDR storage with its AXI interface read/write scheme,and high-precision harmonic analysis.The main research contributions are as follows:1.Top-Level Architecture Design:Based on the AXI bus interconnection,XDMA,and MIG IP cores,along with the concept of update time,a new architecture is designed for multi-channel power analyzers,covering data transmission,reception,computation,storage,and hardware-software interaction.The architecture divides data processing and storage into a real-time computation path based on update time and a harmonic analysis path based on DDR deep storage.Tasks such as power parameter calculation and harmonic analysis are optimally partitioned between hardware and software,with careful storage planning to meet real-time requirements while reducing design complexity,facilitating debugging,maintenance,and future upgrades.2.Real-Time Computation Path Based on Update Time:Beyond the core architecture design,a serial-parallel combined real-time power parameter computation framework supporting multi-card and multi-synchronization sources is implemented for multi-channel power parameter calculation.This framework allows the power analyzer to reuse the same set of parallel computation cores through multiple RAM buffers and ping-pong read/write operations,significantly reducing FPGA logic resource consumption:LUT usage is reduced to only 16.83%of the original;Flip-flop usage drops to 18.514%of the original;DSP utilization is just 13.03%of the original.3.Harmonic Analysis Path Based on DDR Deep Storage:In addition to the core architecture,a linear interpolation-based non-integer downsampling method is explored,proposing both single-point serial and N-point parallel universal architectures tailored to different DDR storage patterns for multi-channel data.The N-point parallel architecture,as a generalized design,improves decimation efficiency by N times while effectively enhancing DDR bandwidth utilization.The power analysis computation system proposed in this thesis has been successfully implemented on a Xilinx xc7vx485tffg1157-1 FPGA and rigorously validated through a practical multi-channel power analyzer project platform.更多还原