【作者】 张翔；

【导师】 唐小琦；

【作者基本信息】 华中科技大学 ， 机械工程， 2024， 硕士

【摘要】 固晶机作为LED生产过程的关键设备,随着LED晶片尺寸微小化和制程高效高精要求不断提高,如何在保证制程精度的情况下,进一步有效提高固晶机效率成为亟待解决的问题。为此,本文结合固晶工艺流程,研究并设计了基于网络规划的LED固晶机生产效率优化方法。根据固晶机晶圆阵列特征分析,提出了以晶片搜索识别定位和固晶时序优化为基础的固晶机效率优化总体方案。通过分析晶圆、图像和转台标定的影响因素,研究了搜晶指导、位姿识别和回正定位的优化方法。结合固晶时序特征,设计了基于搭接网络的时序优化方案。针对晶圆缺陷、图像数据量大等影响晶片识别定位效率和精度的问题,提出了基于分层式搜索和反向校正的晶片识别定位方法。采用有向分层优先级和记忆点策略设计搜晶方法,实现高效搜晶;通过轮廓特征提取和几何矩计算,实现晶片匹配和位姿识别;基于坐标系间几何关系对标定偏差进行反向校正,提高晶片回正定位精度。为了对具有串并行共存、交叉同步关系的固晶时序进行有效优化,提出了基于搭接网络的固晶时序优化方法。基于动作时序特征分析,计算可调整时间;建立单代号搭接网络时序模型对固晶时序充分描述,并通过计算特征时间参数提取动作关键路径;在可调整时间范围中,采用基于渐进寻优的蒙特卡罗法实现最优时序采样求解。在QT开发平台上基于分层架构,采用有限状态机和线程间通信等技术,设计并实现了软件的后台处理层,包括视觉处理和运动控制等功能;基于插件机制与信号-槽机制,设计了人机交互界面,实现了软件的设计开发与优化规划策略的集成。在LED固晶机上使用集成了优化规划策略的控制软件进行固晶功能效果、实际固晶周期统计和不同情况晶圆完整搜晶效果等测试。实验结果表明,对大小为0.16mm×0.48mm的晶片,固晶合格率达到99%以上;平均固晶周期为155.3ms,相较旧版软件提高20%以上;能对典型晶圆完整搜索且仅出现个位次数搜晶中断,综合时产达到23K/H左右,提高21%以上。验证了本文固晶机效率优化方法的有效性。更多还原

【Abstract】 The die-bonding machine is a key equipment in the LED production process.As the size of LED chip becomes smaller and the requirements for high efficiency and precision in the process continue to increase,how to further effectively improve the efficiency of the die-bonding machine while ensuring process accuracy has become an urgent problem to be solved.To this end,combined with the die-bonding process flow,an efficiency optimization method for LED die-bonding machines based on network planning is studied and designed.Based on the analysis of the wafer array characteristics,an overall plan for optimizing the efficiency of the die-bonding machine is proposed,which is based on wafer search and identification and die-bonding timing optimization.By analyzing the influencing factors of wafer,image and turntable calibration,the optimization methods are studied,which aim at wafer search guidance,pose recognition and back-to-alignment positioning.Combined with the timing characteristics of fixing wafers,a timing optimization scheme is designed,which is based on the overlapping network.Aiming at issues such as wafer defects and large amounts of image data that affect the efficiency and accuracy of wafer identification and positioning,a wafer identification and positioning method is proposed,which is based on hierarchical search and reverse correction.The crystal search method is designed using directed hierarchical priority and memory point strategies to achieve efficient crystal search.Chip matching and pose recognition are achieved through contour feature extraction and geometric moment calculation.The calibration deviation is reversed based on the geometric relationship between coordinate systems.Correction to improve the accuracy of wafer alignment and positioning.In order to effectively optimize the die-bonding timing with serial-parallel coexistence and cross-synchronization relationship,a die-bonding timing optimization method is proposed,which is based on overlapping network.Based on action timing feature analysis,the adjustable time between actions is calculated.A single-code overlap network timing model is established to fully describe the die-hardening timing,and the key path of the action is extracted by calculating the characteristic time parameters.In the adjustable time range,the Monte Carlo method based on progressive optimization is used to achieve optimal timing sampling solution.Based on the layered architecture on the QT development platform,using technologies such as finite state machines and inter-thread communication,the background processing layer of the software is designed and implemented,including functions such as motion control and visual processing.Based on the plug-in mechanism and signal-slot mechanism,a human-computer interaction interface is designed to complete the integration of software design implementation and optimization planning strategies.The control software integrated with the optimized planning strategy is used on the LED die-bonding machine to test the die-bonding function effect,the complete die search effect of wafers under different conditions,and the actual die-bonding cycle statistics.Experimental results show that for chips with a size of 0.16mm×0.48 mm,the die-bonding pass rate reaches more than 99%.The average die-bonding cycle is 155.3ms,which is more than 20% higher than the old version of the software.Complete search of typical wafers shows only single-digit search interruptions,and the comprehensive hourly output reached about 23K/H,which is more than 21% higher than the old version of the software.The effectiveness of the die bonding machine efficiency optimization method is verified.更多还原