【作者】 李博；

【导师】 段宝兴； 宋子奇；

【作者基本信息】 西安电子科技大学 ， 电子信息硕士（专业学位）， 2023， 硕士

【摘要】 模数转换器(ADC)作为模拟世界和数字世界的桥梁一直以来在工业界就有着广泛的应用。逐次逼近型(SAR)模数转换器因其结构简单、功耗较低和良好的改进潜力在众多结构中脱颖而出,成为ADC研究的热点。在传感器网络、无线通信等应用场合,ADC通常被要求具有可变精度和采样带宽,根据输入信号的特性来配置ADC,可以避免其浪费过高的精度或采样带宽,从而节约系统的功耗。本文在详细介绍和分析SAR ADC原理的基础上,采用SMIC180nm CMOS工艺,设计了一款12bit 10MS/s和14bit 2.5MS/s两种模式可配置的电荷重分配型SAR ADC。在本文设计中,采用了自顶向下的设计方法。首先,建立了两种模式可配置的“SplitDelta”数字校准SAR ADC的MATLAB模型,验证了数字校准方案的可行性。然后,完成了整体电路的Veriloga-Verilog电路行为级模型建模,快速高效的验证了系统的功能。为了同时满足两种模式对比较器的要求,本文提出了一种可配置的高速高精度比较器架构,采用三级预放大+Latch的级联结构。通过控制第二、三级预放大交叉耦合负载的大小,实现对预放大级速度和增益的配置;通过切换第一级预放大和调节第二、三级镜像基准电流源的大小,实现对整体比较器功耗和噪声的控制。为了适应不同的采样率要求,本文提出了一种同步/异步可配置的SAR控制逻辑结构,通过选择延时内循环回路或外部时钟CLK输入来产生比较器工作时钟。同时,本设计采用的可调延时电路可以完全覆盖由PVT引起的延时变化,采用的动态SAR逻辑单元可以避免输出节点受漏电、串扰等影响,保证了电路的可靠性。关于CDAC设计,本文采用了6-4-3三段式结构,减小了总电容面积。同时,在各分段中均插入了一位冗余位,可以容忍DAC的建立误差以及参考电压的扰动;通过控制高两位权重电容的接入,可以实现CDAC分辨率的配置。在完成关键电路模块设计之后,最后对整体电路进行设计与仿真,完成电路版图绘制,提取寄生参数,完成后仿真验证。本文设计的单个SAR ADC的后仿真校准前结果:12bit 10MS/s模式下,SNDR为53.76d B,SFDR为66.60d B,品质因数FOMW为0.53p J/conv.-step;14bit 2.5MS/s模式下,SNDR为52.95d B,SFDR为63.36d B,品质因数FOMW为7.31p J/conv.-step。后仿真校准后结果:12bit 10MS/s模式下,SNDR为71.80d B,SFDR为85.73d B,品质因数FOMW为67.0f J/conv.-step;14bit 2.5MS/s模式下,SNDR为80.66d B,SFDR为91.78d B,品质因数FOMW为299.6f J/conv.-step。更多还原

【Abstract】 Analog-to-digital converters(ADCs)have been widely used in industry as a bridge between the analogue and digital worlds.Successive approximation(SAR)ADCs stand out from the crowd due to their simplicity,low power consumption and good potential for improvement,and have become a hot topic in ADC research.In applications such as sensor networks and wireless communications,ADCs are often required to have variable accuracy and sampling bandwidth.Configuring an ADC according to the characteristics of the input signal prevents it from wasting too much accuracy or sampling bandwidth,thus saving the power consumption of the system.In this thesis,based on a detailed introduction and analysis of SAR ADC principles,a 12bit10MS/s and 14 bit 2.5MS/s two-mode configurable charge redistribution SAR ADC is designed using the SMIC 180 nm CMOS process.in this thesis,a top-down design approach is adopted.Firstly,a MATLAB model of the "Split-Delta" digitally calibrated SAR ADC with two configurable modes is developed to verify the feasibility of the digital calibration scheme.Then,a Veriloga-Verilog circuit behavioural level model of the overall circuit was completed to quickly and efficiently verify the functionality of the system.In order to meet the requirements of both modes for the comparator,a configurable high-speed,highprecision comparator architecture is proposed in this thesis,using a three-stage preamplification + Latch cascade structure.The configuration of the speed and gain of the preamplification stage is achieved by controlling the size of the second and third preamplification cross-coupling loads;the control of the overall comparator power consumption and noise is achieved by switching the first pre-amplification stage and adjusting the size of the second and third mirror reference current sources.To accommodate different sampling rate requirements,this thesis proposes a synchronous/asynchronous configurable SAR control logic structure that generates the comparator operating clock by selecting either a delayed internal loop or an external clock CLK input.At the same time,the adjustable delay circuit used in this design can completely cover the delay variation caused by the PVT,and the dynamic SAR logic unit used can avoid the output node from leakage and crosstalk,ensuring the reliability of the circuit.Regarding the CDAC design,this thesis adopts a 6-4-3 three-segment structure to reduce the total capacitance area.At the same time,one redundant bit is inserted in each segment,which can tolerate the establishment error of the DAC as well as the disturbance of the reference voltage;the configuration of the CDAC resolution can be achieved by controlling the access of the high two weighting capacitors.After the key circuit modules are designed,the overall circuit is finally designed and simulated to complete the circuit layout drawing,extract parasitic parameters and complete post-simulation verification.Pre-calibration results of the single SAR ADC designed in this thesis: SNDR of 53.76 d B,SFDR of 66.60 d B and quality factor FOMW of 0.53 p J/conv.-step in 12 bit 10MS/s mode;SNDR of 52.95 d B,SFDR of 63.36 d B and quality factor FOMW of 7.31 p J/conv.-step in14 bit 2.5MS/s mode.Post-simulation calibration results: SNDR of 71.80 d B,SFDR of85.73 d B and quality factor FOMW of 67.0f J/conv.-step in 12 bit 10MS/s mode;SNDR of80.66 d B and SFDR of 80.66 d B in 14 bit 2.5MS/s mode.In 14 bit 2.5MS/s mode,the SNDR is 80.66 d B,the SFDR is 91.78 d B and the quality factor FOMW is 299.6f J/conv.-step.更多还原