【作者】 刘鹏；

【导师】 唐路； 蒋颖丹；

【作者基本信息】 东南大学 ， 电子与通信工程（专业学位）， 2022， 硕士

【摘要】 随着现代无线通信技术的发展,出现了不同类型的通信标准去适配不同的应用场景,因此能够同时兼容多标准的宽带无线收发机芯片逐渐成为研究热点。本文主要研究并设计了应用于锁相环频率综合器中的宽带压控振荡器(Voltage Controlled Oscillator,VCO)与电流模逻辑(Current Mode Logic,CML)高速预分频器电路,该频率综合器可为宽带收发机提供覆盖7 GHz以下的本振信号。本文详细分析了宽带VCO及CML高速预分频器的工作机理与电路设计方法,然后进行版图设计并给出了电路的后端仿真结果,最后对设计的宽带VCO进行流片测试。对于宽带VCO的设计,本文首先分析了多种实现宽带VCO的技术方向,最后基于130-nm CMOS工艺设计了工作频率为7 GHz～14 GHz的电耦合的模式切换双模VCO。在电路设计部分,首先介绍了电感的选取、高Q值变容管设计、8比特电容阵列设计、模式切换开关网络设计、可调尾电流源和输出缓冲电路的设计,最后基于Lesson模型对本课题的宽带VCO做了整体相位噪声优化。后端仿真结果表明宽带VCO的调谐范围为7.04GHz～14.31 GHz,为后续的芯片测试预留了频率裕量,在工作频段内其相位噪声优于-114.6d Bc/Hz@1MHz。芯片测试结果表明宽带VCO的调谐范围为6.49 GHz～13.84 GHz,相对带宽为72.1%,相位噪声在工作频段内优于-111.4 d Bc/Hz@1MHz。对于高速预分频器的设计,本文首先介绍了常用的分频器类型并对其工作模型进行了理论分析,最终确定采用CML分频器作为本课题宽带VCO的后级预分频器电路,以此产生四路正交信号作为本振输出。在电路设计部分,首先确定了CML二分频器的电路结构,再对分频器的关键指标进行了分析,最后阐述了静态CML触发器、时钟偏置电路和输出缓冲电路的设计。CML预二分频器与宽带VCO的联合仿真结果表明在工作频段内分频器工作正常,且分频器输出幅度大于800 m V,满足预期的设计指标。更多还原

【Abstract】 With the development of modern wireless communication technology,different types of communication standards have emerged to adapt to different application scenarios,so broadband wireless transceiver chips that are compatible with multiple standards at the same time have gradually become a research hotspot.This article mainly studies and designs the wideband Voltage Controlled Oscillator(VCO)and Current Mode Logic(CML)high-speed prescaler circuits used in the phase-locked loop frequency synthesizer,which provides local oscillator signals covering sub-7 GHz for wideband transceivers.This article analyzes the mechanism and circuit design of the wideband VCO and CML high-speed prescaler,and then carries out the layout design and gives the back-end simulation results of the circuit.Finally,the designed wideband VCO is tested.For the design of wideband VCO,this article first analyzes various technical directions for realizing wideband VCO,and finally designs an electrically coupled mode-switching dual-mode VCO with an operating frequency of 7 GHz to 14 GHz based on a 130-nm CMOS process.In the circuit design part,the selection of the inductor,the design of the high-Q value varactor,8-bit capacitor array,mode-switching network,adjustable tail current source and the output buffer circuit are first introduced.The wideband VCO is optimized for overall phase noise according to Lesson model.The back-end simulation results show that the wideband VCO has a tuning range of 7.04 GHz to 14.31 GHz,which reserves a frequency margin for subsequent chip testing,and its phase noise in the operating frequency band is better than-114.6 d Bc/Hz@1 MHz.The chip test results show that the tuning range of the wideband VCO is 6.49 GHz～13.84 GHz,the relative bandwidth is 72.1%,and the phase noise is better than-111.4 d Bc/Hz@1 MHz in the working frequency band.For the design of high-speed prescaler,this article firstly introduces the commonly used frequency divider types and theoretically analyzes their working models,and finally decides to use CML frequency divider as the post-stage prescaler circuit of the wideband VCO in this subject.In this way,four quadrature signals are generated as the local oscillator output.In the circuit design part,the circuit structure of the CML divide-by-two frequency divider is determined first,and then the key indicators of the frequency divider are analyzed.Finally,the design of the static CML flipflop,clock bias circuit and output buffer circuit are described.The co-simulation results of the CML prescaler and the wideband VCO show that the divider works normally in the working frequency band,and the output amplitude of the divider is greater than 800 m V,which meets the expected design specifications.更多还原