【作者】 张娟；

【导师】 陆生礼； 李海松；

【作者基本信息】 东南大学 ， 集成电路工程（专业学位）， 2022， 硕士

【摘要】 随着智慧交通的发展,车道线检测技术为高级驾驶辅助系统(ADAS)提供有效的路径规划,是推动ADAS发展的关键技术。然而相较于传统算法,基于深度学习的车道线检测算法具有庞大的参数量和计算量,在车载终端设备上部署高准确率的车道线检测算法,面临着存储资源和算力不足等问题。为了满足车道线检测系统在终端设备的高实时性、高准确率和小型化等要求,基于软硬件协同设计来实现高效的车道线检测算法具有重要的实用价值。本文设计了一种基于深度学习的轻量级车道线检测算法,通过使用残差网络和通道注意力机制来加强网络学习能力;使用行分类策略来减少计算量;添加辅助训练网络,并设计结构和分类损失函数对各分支网络进行监督,保证了在不影响推理速度的同时,更高效地提取车道线特征;使用Do Re Fa量化算法对模型进行4-bit量化来压缩模型,更有利于硬件部署。硬件部分设计基于FPGA的神经网络加速器,采用特征图全片上存储模式来减少对片外内存的访问,极大提高了检测速度。最后,本文基于FPGA平台搭建车道线检测系统,将量化的车道线检测算法和硬件加速器在Zynq开发板上进行验证,实现了车道线的实时检测。实验结果表明,本文对检测精度和检测速度进行权衡,车道线检测算法在Tu Simple数据集上达到96%的准确率,在CULane数据集上达到71.24%的检测精度评价指标,在NVIDIA Geforce RTX 2080Ti上达到261FPS的平均速度。车道线检测算法和硬件加速器部署到Zynq-7100开发板上,以31.25FPS的检测速度完成对数据集图像的检测。本文的研究对基于深度学习的车道线检测算法在终端设备的部署具有一定的参考意义。更多还原

【Abstract】 With the development of intelligent transportation,lane detection technology provides effective path planning for Advanced Driver Assistance System(ADAS),which is a key technology to promote the development of ADAS.However,compared with the traditional algorithm,the lane detection algorithm based on neural network has a large number of parameters and a large amount of calculation.Therefore,the deployment of the lane detection algorithm with high accuracy on the vehicle terminal equipment is faced with problems such as insufficient storage resources and computing power.In order to meet the requirements of high real-time,high accuracy and miniaturization of vehiclemounted terminal lane detection system,it is of great practical value to realize efficient lane detection algorithm based on software and hardware co-design.In this paper,a lightweight lane detection algorithm based on deep learning is designed to enhance the network learning ability by using residual network and channel attention mechanism.The row classification strategy is used to reduce the computation.The auxiliary training network was added,and the structure and classification loss function were designed to supervise each branch network,which ensured that the lane feature could be extracted more efficiently without affecting the inference speed.Do Re Fa quantization algorithm is used to compress the model by 4-bit quantization,which is more conducive to hardware deployment.A neural network hardware accelerator based on FPGA is designed.The feature map full on-chip memory mode is adopted to reduce the access to offchip memory,which greatly improves the detection speed.Finally,this paper builds a lane detection system based on FPGA platform,verifies the quantitative lane detection algorithm and hardware accelerator on Zynq development board,and realizes the real-time lane detection.Experimental results show that the proposed algorithm achieves 96% accuracy on Tu Simple dataset and 71.24% accuracy on CULane dataset by balancing detection accuracy and detection speed.Achieves an average speed of 261 FPS on the NVIDIA Geforce RTX 2080 Ti.The lane detection algorithm and hardware accelerator are deployed on Zynq-7100 development board,and the detection speed of data set image is 31.25 FPS.The research content of this paper has a certain reference significance for the deployment of lane detection algorithm based on deep learning in terminal equipment.更多还原