【作者】 刘翔；

【导师】 李芹；

【作者基本信息】 东南大学 ， 电路与系统， 2020， 硕士

【摘要】 近些年来,随着第五代移动通信(5G)技术的蓬勃发展和人们对高速短距离通信需求的不断提升,毫米波(30～300GHz)由于具有波长短、频谱资源丰富等特点,成为了当今行业内学者研究的热点频段。CMOS工艺因其集成度高、低成本、工艺成熟、能与基带工艺相集成等优点,有着广大的应用前景。基于CMOS工艺的毫米波集成电路芯片越来越多地被设计出来。作为无线收发机的核心组成模块,锁相环频率综合器电路直接决定了整个收发系统的性能优劣。锁相环系统中的核心模块为压控振荡器与分频器,这两个模块工作在系统的最高频率上,功能是给整个射频收发系统提供稳定的本振信号。它们的性能指标如工作频率、调谐范围、相位噪声、功耗等将直接决定锁相环系统乃至整个收发机能否正常工作。于是,本文基于40nm CMOS工艺设计了两个应用于毫米波锁相环的工作频率为100GHz的二分频器。首先设计的是一款基于注入锁定的LC型二分频电路。论文对几种注入锁定模型及其锁定范围作了详细的分析,并介绍了两种注入方式(直接注入与尾电流注入)的注入锁定分频器,分析了分频器的关键性能指标。在这基础之上,设计了直接注入式的LC型二分频器电路,并设计了共源极差分放大电路结构的缓冲电路。电路在传统直接注入型ILFD基本结构的基础之上,作了如下一些改进:单端注入改为双端注入、注入管加上衬底偏置等以及相关MOS管参数的合理选取,以此来提高电路的工作频率、扩大注入锁定频率范围和减小功耗等。前仿真对电路的分频功能进行了验证。由于本次所设计的分频器工作频率较高,工艺库中所提供的无源器件模型已较为不准确,因此需要通过电磁场仿真软件自行设计相应的关键无源器件电感。在详细介绍布局布线时需要考虑的一些规则的基础之上设计了电路的版图并优化以减小寄生、干扰和失配。在经过物理验证之后,对电路的寄生参数进行了提取。首先是对电路的核心MOS管及其走线部分的寄生电阻和寄生电容进行了单独地提取,然后将各节点所提取的寄生电阻和寄生电容值代入到原来的原理图进行相应的后仿真。接着对电路输入输出的关键长走线部分和焊盘部分的寄生电感和互感进行了提取并代入原电路进行后仿真。对电路在各种不同的仿真条件下进行了后仿真。结果显示,在最差条件(SS工艺角、125℃)下,电路可以实现正确分频的范围为:92GHz～106GHz。电源电压0.9V情况下,核心电路功耗为14.9mW。核心电路面积为61μm×131μm。电路成功实现了高频率、宽锁定范围、低功耗等设计指标。接着设计的是一款基于D触发器的静态电流模式逻辑二分频器电路。在对电流模式逻辑分频器几种结构分析比较的基础之上,设计了静态结构的二分频器及相应的缓冲放大电路。为提高电路工作频率,采用了电感并联峰化等技术。通过合理设置电路的自由振荡频率点、合理设计电感、合理选取MOS管的类型和尺寸,提高了电路的工作频率,扩大了锁定范围。分别对核心电路与带缓冲器的整体电路作了前仿真以验证电路的分频功能。同样,自行设计了无源器件电感。在考虑布版注意事项和避免寄生效应的基础上设计了电路的版图。对核心电路和输入输出关键长走线进行了寄生参数的提取之后,对电路在各种不同的仿真条件进行了后仿真,结果显示,在最差条件(SS工艺角、125℃)下,电路可以实现正确分频的范围为72～110GHz。给出了相应的输入灵敏度曲线和电路功耗曲线。电源电压1.8V情况下,核心电路功耗为25.6mW。核心电路面积为86μm×150μm。幅度为300mV的信号输入时的分频范围为72～110GHz。最后给出了两款电路的测试方案和两款电路的性能对比。更多还原

【Abstract】 In recent years,with the vigorous development of the fifth generation mobile communication(5G)technology and the continuous improvement of people’s demand for high-speed and short-range communication,millimeter-wave(30～300GHz)has become a hot band for researchers in the industry because of its rich spectrum resources and short wavelength.CMOS technology has a broad application prospect because of its advantages of high integration,low cost,mature technology and integration with baseband circuits.More and more millimeter-wave chips based on CMOS process have been designed.As the core module of wireless transceiver,frequency synthesizer directly influences the performance of the whole transceiver system.The core modules of PLL system are voltage controlled oscillator and frequency divider which work at the highest frequency of the system.Their performance,such as operating frequency,tuning range,phase noise and power consumption,will directly determine whether the PLL system and the whole transceiver can work normally.Therefore,based on 40 nm CMOS technology,two 100 GHz frequency dividers applied in millimeter-wave PLL are designed in this thesis.First,a LC frequency divider circuit based on injection locking is designed.In this thesis,several injection locking models and their locking ranges are analyzed in detail.Two injection modes(direct injection and tail current injection)are introduced,and the key performance indexes of the divider are analyzed.On this basis,a direct injection LC type frequency divider is designed,and a common source differential amplifier circuit is designed.Based on the basic structure of traditional direct injection type ILFD,some improvements are made as follows: single end injection is replaced by double end injection,injection tube plus substrate bias,and reasonable selection of related MOS transistor parameters,so as to improve the working frequency,expand the injection locking frequency range and reduce power consumption.The pre-simulation verifies the frequency division function of the circuit.Due to the high working frequency of the frequency divider,the passive component model provided in the process library is not accurate.Therefore,it is necessary to design the corresponding key passive component inductance by electromagnetic field simulation software.Based on the detailed introduction of some rules to be considered in layout and routing,the layout of the circuit is designed and optimized to reduce parasitic,interference and mismatch.After physical verification,the parasitic parameters of the circuit are extracted.Firstly,the parasitic resistance and capacitance of the core MOS transistor and its wiring part are extracted separately,and then the parasitic resistance and capacitance extracted from each node are substituted into the original schematic diagram for corresponding post simulation.Then the parasitic inductance and mutual inductance of the key long wiring part and pad part of the circuit input and output are extracted and replaced into the original circuit for post simulation.The post simulation of the circuit is carried out under different simulation conditions.The results show that under the worst condition(SS process angle,125℃),the correct frequency division range is 92GHz～106GHz.The power consumption of the core circuit is 14.9mW with a 0.9 supply voltage.The area of the core circuit is61 μ m×131 μ m.High frequency,wide lock-in range and low power consumption are realized successfully.Then a static current-mode logic divider based on D flip flop is designed.Based on the analysis and comparison of several structures of current-mode logic frequency divider,a static structure divider is designed.In order to broaden the bandwidth of the circuit,inductor parallel-peaking is adopted.By reasonably setting the free oscillation frequency point of the circuit,reasonably designing the inductance and selecting the type and size of MOS transistor,the working frequency of the circuit is increased and the locking range is expanded.The whole circuit with buffer are pre simulated to verify the frequency division function of the circuit.Similarly,the passive inductor is designed by ourselves.The layout of the circuit is designed based on the considerations of layout and avoidance of parasitic effect.After the parasitic parameters of the core circuit and the key input and output lines are extracted,the post simulation of the circuit under various simulation conditions is carried out.The results show that the correct frequency division range of the circuit is 72 ～110GHz under the worst condition(SS process angle,125 ℃).The corresponding input sensitivity curve and circuit power consumption curve are given.The power consumption of the core circuit is 25.6 mW with a 1.8 supply voltage.The area of the core circuit is 86 μm × 150 μm.The frequency division range is 72～110 GHz with the 300 mV signal input.Finally,the test scheme of the two circuits and the performance comparison of the two circuits are given.更多还原