【作者】 刘源；

【导师】 张有润；

【作者基本信息】 电子科技大学 ， 工程硕士（专业学位）， 2021， 硕士

【摘要】 随着物联网时代的即将到来,自动驾驶、智能视觉等领域逐渐发展起来。CMOS图像传感器作为这些领域重要的一双“眼睛”,如何提高CMOS图像传感器的帧率和分辨率就成了如今学术界以及产业界研究的热点。模数转换器(ADC)作为CMOS图像传感器中的重要模块,它的速度与精度直接决定了CMOS图像传感器的性能。随着集成电路制程工艺的越来越先进,逐次逼近ADC(SAR ADC)与流水线ADC(Pipelined ADC)以及Sigma-Delta ADC等相比,它不需要复杂设计,消耗的功耗比较小,芯片版图面积小,另外逐次逼近ADC具有中高精度以及中等的速度。所以从总体上看,逐次逼近ADC是比较适用于现在的CIS的研究与设计。本文基于CMOS图像传感器应用背景,使用HLMC 55纳米的制程工艺,研究了一种逐次逼近ADC,它的精度是12位,速度是120KS/s。本论文研究了逐次逼近ADC的常见结构,其核心模块电路包括三个部分,本文也是主要讲述了这三个部分电路的设计。在进行DAC电路的设计时,分析了分段电容型逐次逼近ADC的优缺点。确定了差分两步结构DAC电容阵列,将电容阵列分为高6位组以及低6位组,按照上下排列的位置,分别耦合在比较器的正相端与反相端。针对于采样开关,本文使用了栅压自举的电路结构,比较有效的减小采样误差。对于整体SAR ADC系统来说,DAC的设计减小了芯片的面积与功耗。在设计比较器时,使用一种新结构的可再生比较器,节省了比较过程消耗的能量,提高了比较速度。在对SAR逻辑控制电路设计时,研究了多种类型触发器,最终采用了一种新型逻辑单元,只有高6位组的电容参与了对输入信号的采样,低6位组的电容没有参与,有效的降低了电路的功耗并且提高了电路的工作速度。设计完主要的电路模块以后,对整个逐次逼近SAR ADC进行仿真。测试ADC的DNL为-0.3/0.3LSB,INL为-0.3/0.42LSB,具有良好的静态性能。整个逐次逼近ADC采用双电源供电,数字部分是1.5V,模拟部分是3.3V,系统的时钟频率为2MHz。前仿结果表示,在输入摆幅为1.65V,频率为585.94Hz的正弦波信号,采样率为120KHz的情况下,ENOB是11.78位,具有良好的动态性能。更多还原

【Abstract】 With the appearance of the Internet of Things epoch,for example,autopilot area and intelligent vision area have gradually developed.CMOS image sensor is an important pair of "eyes" in these fields.How to increase the frames per second and resolving ratio of CMOS image sensor has become a hot spot in the scholastic and industrial groups.The analog-to-digital converter(ADC)is an important composition in the CMOS image sensor,and its speed and precision immediately decide the capability of the CMOS image sensor.As the integrated circuit process craft becomes more and more advanced,the successive approximation ADC(SAR ADC)is compared with the pipeline ADC(Pipelined ADC)and Sigma-Delta ADC.It does not require complex design,consumes less power,and the chip layout area is small,and the successive approximation ADC has moderate high accuracy and moderate velocity.On the whole,the successive approximation ADC is more appropriate for the current CIS research and design.Based on the application background of CMOS image sensor,this thesis uses HLMC 55 nm process technology to study a successive approximation ADC,its accuracy is 12 bits,and the speed is 120KS/s.This thesis studies the common structure of successive approximation ADCs.Its core module circuit includes three portions.This thesis has devised three main circuit modules.In the creation of the DAC circuit,the merits and defects of the segmented capacitor type successive approximation ADC are analyzed.The differential two-step structure DAC capacitor arrange is confirmed,and the capacitor arrange is separated into a high 6-bit group and a low 6-bit group.According to the upper and lower positions,the two sides are linked to the two ends of the voltage comparator,one positive phase port and one negative phase port.Aiming at the sampling disjunctor,this article uses the gate voltage bootstrap circuit structure,it validly reduce the sampling error.For the overall SAR ADC system,the design of the DAC decreases the space and energy expansion of the microchip.When designing the comparator,a new structure of the regenerative comparator is used,which saves the energy consumed in the comparison process and increases the comparison rate.When designing the SAR logic control circuit,researched many types of flip-flops,and finally adopted a new type of logic unit.Only the capacitance of the high 6-bit group participates in the sampling of the input signal,and the capacitance of the low 6-bit group does not participate,which validly decreases the circuit energy dissipation and ameliorates the working rate of the circuit.After the main circuit modules are designed,the whole successive approximation SAR ADC is simulated.The DNL of the tested ADC is-0.3/0.3LSB,and the INL is-0.3/0.42 LSB,which has good static performance.The whole successive approximation ADC adopts dual power supply,the digital part is 1.5V,the analog part is 3.3V,and the system clock rate is 2MHz.The previous emulation result reveals that when the import sine wave range is 1.65 V,the rate is 585.94 Hz,and the sampling rate is 120 KHz,the ENOB is 11.78 bits,which has good dynamic performance.更多还原