【作者】 孙斌；

【导师】 王新胜；

【作者基本信息】 哈尔滨工业大学 ， 集成电路工程（专业学位）， 2019， 硕士

【摘要】 近年来,航天事业进入了高速发展的新时期。航天活动的强度、成本与任务时长都大幅度提高,因此对航天产品的可靠性要求愈加严格。相对于其他材料的航天设备,集成电路器件对太空的异常环境极度敏感,极容易受其影响,异常环境导致器件参数偏移、功能紊乱甚至永久性损伤。因此保证航天电子系统尤其是集成电路器件的可靠性是保证航天产品可靠性的关键。随着高速并行计算能力的提高,深度学习的神经网络理论在多个领域的应用有了令人惊艳的表现,基于神经网络的集成电路可靠性模型成为新兴起的研究热点,设计一种基于神经网络的宇航集成电路器件的失效诊断系统对保障航天安全有重要意义。本文采取理论研究、系统框架构建、软件实现、硬件实现、验证实验依次进行的设计思路。首先,研究了超大规模集成电路的主要失效机理,分析了失效过程、诱因和参数的相对变化关系,选择能够反映器件失效状态的关键参数作为特征参数。在此基础上,设计待测系统电路,待测系统包括待测芯片、特征参数采集器件以及通用外围电路。采集器件获取待测芯片的特定参数作为特征参数并传输给失效诊断系统进行分析。其次,研究了神经网络的模式识别原理,设计了一种基于反向传播型神经网络的集成电路芯片失效诊断系统,依托失效诊断系统,对特征参数进行分析,预测待测器件的工作状态。失效诊断系统主要包括特征参数处理模块、神经网络训练平台和神经网络诊断模型。特征参数处理的功能是将特征参数处理成适合神经网络诊断模型输入的形式;使用Verilog HDL设计,并在FPGA上实现。神经网络训练平台的功能是通过机器学习的方法训练神经网络参数,从而使神经网络诊断模型能够更好地分析特征参数;使用Python进行设计,并通过软件实现。神经网络诊断模型的功能是分析特征参数并预测待测系统的工作状态;使用Verilog HDL设计,并在FPGA上实现。最后,对基于神经网络的故障诊断系统进行验证实验。验证实验分两部分进行:一部分是失效诊断系统独立验证实验,另一部分是失效诊断系统与待测系统协同实验。独立验证实验将CMOS静态存储单元电路高温仿真数据和JFM4VSX55RT型FPGA的三温测试数据作为特征参数,对目标电路、目标器件进行失效状态诊断。当训练次数超过2000次时,失效状态诊断对CMOS静态存储单元电路和JFM4VSX55RT型FPGA的高温失效诊断准确率稳定超过97%。协同验证实验中,选择DSP芯片的电流作为特征参数,对待测芯片的失效状态进行诊断。实验结果表明,对待测系统特征参数的采集频率达2.5MHz,诊断周期30μs,对小样本高温失效诊断的准确度接近100%。更多还原

【Abstract】 In recent years,the space industry has entered a new period of rapid development.The intensity,cost and mission duration of space activities have all been greatly increased,so the need for reliability of space products have become more and more stringent.Compared with other space equipment,integrated circuit devices are extremely sensitive to the abnormal environment in space,which leads to parameter deviation,functional disorder and even permanent damage of IC devices.Therefore,to ensure the reliability of aerospace electronic systems,especially integrated circuit devices,is the key to ensure the reliability of aerospace products.It is very important to design a failure diagnosis system for aerospace integrated circuit devices.Meanwhile,with the mature theory of machine learning and high-speed parallel computing,the age of big data has come.The application of neural network in various fields has become a general trend,which injects new impetus into the research of integrated circuit reliability.The design idea adopted in this paper is that theoretical research,system framework construction,software implementation,hardware implementation and verification experiments are carried out successively.Firstly,the main failure mechanisms of VLSI are studied,and the relative changes of failure process,inducement and parameters are analyzed.The key parameters that can reflect the failure state of devices are selected as characteristic parameters.On this basis,the circuit of the system under test is designed.The system under test includes chip under test,feature parameter acquisition device and general peripheral circuit.The acquisition device takes the specific parameters of the chip under test as characteristic parameters and transmits them to the failure diagnosis system for analysis.Secondly,the theory of pattern recognition is studied,and an integrated circuit chip failure diagnosis system based on back propagation neural network is designed.Through the fault diagnosis system,the fault characteristic parameters are analyzed to predict the working state of the device under test.The fault diagnosis system mainly includes characteristic parameter processing module,neural network training platform and neural network diagnosis model.The function of feature parameter processing is to process feature parameters into a form suitable as a neural network diagnostic model input.The characteristic parameter processing module is designed by Verilog HDL and implemented on FPGA.The function of neural network training platform is to train neural network parameters by machine learning so that the neural network diagnostic model can better analyze the characteristic parameters.The neural network training platform is designed in Python and implemented in software.The function of neural network diagnostic model is to analyze the characteristic parameters and predict the working state of the system under test.The neural network diagnosis model is designed by Verilog HDL and implemented on FPGA.Finally,the fault diagnosis system based on neural network is verified and tested.The validation experiment is divided into two parts: one is the independent validation experiment of the failure diagnosis system,and the other is the collaborative validation experiment of the failure diagnosis system and the system under test.In the independent verification experiment,high temperature simulation data of CMOS static storage unit circuit and JFM4VSX55 RT FPGA tri-temperature test data were taken as characteristic parameters to diagnose the failure state of target circuit and target device.When the number of training times exceeds 2000,the accuracy rate of failure state diagnosis for CMOS static storage unit circuit and JFM4VSX55 RT FPGA is stable over 97%.The current of the DSP chip was selected as the Characteristic parameter in the collaborative verification experiment,and the working state of the chip under test was diagnosed.The experimental results show that the acquisition frequency of the characteristic parameters is 2.5MHz,the diagnosis period is 30μs,and the diagnostic accuracy for high temperature failure for small samples is close to 100%.更多还原