【作者】 李强；

【导师】 李振荣； 缑佳禛；

【作者基本信息】 西安电子科技大学 ， 工程硕士（专业学位）， 2020， 硕士

【摘要】 随着移动终端时代的到来,SoC技术得到了更加广泛的应用和发展,为满足用户对移动终端产品不断增加的功能需求,SoC芯片中所集成的处理器子系统和IP核也越来越多,如何在保证各个子系统正常协作的基础上,最大程度地提升SoC的整体性能,将直接影响到用户对产品的青睐程度。为此,SoC芯片设计人员需要尽早地收到芯片性能评估数据的反馈,以赶在产品的上市窗口期内完成对SoC系统整体性能的优化和改善。但是目前基于SoC的性能分析和测试大多在芯片流片后进行,无法给芯片设计人员提供及时有效的性能数据且容易因流片后性能测试失败无法补救导致成本的浪费。而对于芯片流片前的性能分析,目前业内还没有形成一个统一完善的标准和规范,现阶段常用的硅前性能分析方法如模型建立和动态仿真,也均由于精度不够或效率太低而使得系统性能分析的完备性不足。基于SoC芯片功能验证的思路,并通过借鉴硅前动态仿真的性能分析方法,本文提出了一套用于LPDDR4内存控制器系统的高效性能分析方案。该方案首先对内存控制器系统的架构和数据通路进行了分析,并给出了衡量系统性能的性能指标及最终的性能优化目标。随后基于对内存控制器系统内部所有性能优化逻辑的分析,提取出了影响该系统性能的所有软件配置参数和硬件设计参数。然后重点开发了用于对这些性能参数进行性能验证的自动化性能验证环境,该环境不仅包含可用于对测试用例进行动态仿真的UVM验证平台,还集成了基于Python开发的自动化性能分析工具。最后应用该高效的自动化性能验证环境以及为模拟SoC多端口数据传输而编写的模块级测试用例,完成了对内存控制器系统中所有软件配置参数和硬件设计参数的性能分析和优化,得出了这些参数对内存控制器系统性能的影响规律,并通过与芯片设计人员的反馈最终完善了内存控制器系统在不同数据传输场景下的软件配置,修复了影响系统性能瓶颈的硬件设计。本文基于提出的自动化性能分析方案,充分分析了影响系统性能的关键设计,提取了所有相关的软硬件参数,开发了自动化性能验证环境,并完成了所有相关参数的性能完备性验证,同时提高了性能分析的效率和自动化水平,最终使SoC系统的整体性能得到了明显提升。其中,在参与性能评估的SoC四个子系统中,CPU的平均吞吐量提升比例最大,达到了119.4%,OCH的平均吞吐量也实现了11.9%的提升,最终四个子系统的总吞吐量实现了28%的整体性能提升。此外,优化后四个子系统在同时进行数据传输时的平均延迟时间也均实现了35%以上的性能提升比例,其中CPU的提升比例最大,达到了41.7%。系统整体延迟时间的统计分布图呈现了明显的左移,其中统计数量最多的延迟时间值由优化前的210ns变为了优化后的120ns,性能提升比例为42.9%。更多还原

【Abstract】 With the advent of the mobile terminal era,SoC technology has been more widely applied and developed.In order to meet users’ increasing functional requirements for mobile terminal products,more and more processor subsystems and IP cores are integrated in SoC chips.How to improve the overall performance of the SoC to the maximum extent on the basis of ensuring the normal cooperation of the various subsystems will directly affect the user’s favor for the product.For this reason,SoC chip designers need to receive feedback from the chip performance evaluation data as early as possible in order to complete the optimization and improvement of the overall performance of the SoC system within the market window of the product.However,most of the current SoC-based performance analysis and testing is performed after the chip is taped out,so it is impossible to provide chip designers with timely and effective performance data,and it is easy to lose costs due to failure to perform performance test after taped out.As for the performance analysis before chip tape-out,the industry has not yet formed a unified and complete standard and specification.At present,the commonly used pre-silicon performance analysis methods such as model building and dynamic simulation are also caused by insufficient accuracy or low efficiency.The system performance analysis is incomplete.Based on the idea of SoC chip function verification,and by drawing on the performance analysis method of dynamic simulation before silicon,this paper proposes a set of efficient performance analysis schemes for LPDDR4 memory controller system.This solution first analyzes the architecture and data path of the memory controller system,and gives performance indicators to measure system performance and performance optimization goals.Then based on the analysis of various performance optimization logics inside the memory controller system,all software configuration parameters and hardware design parameters that affect the performance of the system were extracted.Then focused on developing an automated performance testing environment for performance verification of these performance parameters.This environment not only integrates a UVM verification platform that can be used for dynamic simulation of test cases,but also integrates automated performance analysis tools based on Python.Then applied this efficient automated performance test environment and the module-level test cases written to simulate SoC multi-port data transmission,and completed the performance analysis and optimization of all software configuration parameters and hardware design parameters in the memory controller system.The influence of these parameters on the performance of the memory controller system,and through feedback with the chip designer,the software configuration of the memory controller system under different data transmission scenarios was finally improved,and the hardware design that affected the system performance bottleneck was repaired.Based on the proposed automated performance analysis scheme,this paper fully analyzes the key designs that affect the performance of the system,extracts all relevant hardware and software parameters,develops an automated performance verification environment,and completes the performance completeness verification of all relevant parameters,while improving the efficiency and automation level of performance analysis and finally make the overall performance of the SoC system significantly improved.Among them,among the four SoC subsystems participating in performance evaluation,the average CPU throughput increased the most,reaching 119.4%,the average throughput of OCH also achieved a 11.9% increase,and finally the total throughput of the four subsystems was achieved 28% overall performance improvement.In addition,after the optimization,the average delay time of the four subsystems when performing data transmission at the same time also achieved a performance improvement ratio of more than 35%,of which the CPU improvement ratio was the largest,reaching 41.7%.The statistical distribution of the overall delay time of the system showed a significant left shift.The delay time value with the largest number of statistics changed from 210 ns before optimization to 120 ns after optimization,and the performance improvement ratio was 42.9%.更多还原