【作者】 王琰；

【导师】 刘志伟；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2020， 硕士

【摘要】 在集成电路产业中,静电放电(Electrostatic Discharge,ESD)失效在总失效模式中占据了很大比例,造成了大量的经济损失。对于先进纳米级集成电路工艺,电源电压较低,器件的栅极氧化层厚度不断减薄,使得器件击穿电压值更低,进而导致了ESD设计窗口更加狭窄,增加了ESD防护设计的难度。本论文对先进纳米级集成电路工艺下的ESD器件和全芯片防护做了研究和总结,主要内容如下:(1)研究了先进纳米级集成电路工艺下的常用ESD防护器件,包括二极管、绝缘栅型场效应晶体管(MOSFET)和可控硅整流器(SCR)。本文基于55nm CMOS工艺,通过对器件重要参数进行调整,结合测试结果对器件特性进行分析和总结,并根据器件特性提出了相应的ESD全芯片保护方案,为后续ESD器件设计提供了参考。(2)在21nm CMOS工艺下,其设计窗口为:I/O端口的设计窗口为1.32V-3.7V,电源端口的设计窗口为2.8V-7V。针对21nm CMOS工艺狭窄的设计窗口,本文设计了DCSCR、DTSCR和二极管串三种器件以及基于三种器件的全芯片防护方案。首先,本文通过堆叠的方式改变DCSCR器件的触发电压使其能够符合不同的设计窗口,其中两个DCSCR堆叠的器件能够满足电源设计窗口,可以用于电源端口的防护;其次,本文还提出了一种改进的版图方式使得DCSCR器件的导通电阻降低了1.5Ω;最后,为了使DTSCR器件更容易开启,增大了DTSCR的P阱电阻,使其能满足I/O端口的设计窗口,可以用于I/O端口的防护。(3)对于先进纳米级工艺的双向电路端口,通常需要ESD防护器件具有双向的电流泄放能力。为满足上述设计需求,本文提出了一种新型RC电路触发的双向ESD保护电路。该电路采用二极管整流电路与MOSFET整流电路并联构成改进的桥式整流电路,可以将I/O端口的正、负电压转换成一个单极电压并输入到RC触发电路,进而使得钳位NMOS器件开启并泄放ESD电流。本文通过SPICE仿真验证了其可以用于I/O端口有正、负电压输入的情况下的双向ESD防护。更多还原

【Abstract】 In integrated circuit industry,Electrostatic Discharge(ESD)failures account for a large proportion of the total failure modes,causing a lot of economic losses For advanced nanoscale integrated circuit processes,the power supply voltage is low,thinner gate oxides lead to lower breakdown voltages.As a result,the ESD design window has become much narrower and the design for ESD protection has become more difficult.In this article,the research of ESD protection devices and full chip ESD protection in nanoscale processes are summarized as follows:(1)This paper makes a research of the traditional ESD protection devices commonly used in advanced nanoscale integrated circuit processes,which include diode,MOSFET and SCR.By adjusting the important parameters of the device,the working mechanism and physical mechanism of three traditional ESD protection devices are analyzed and summarized in combination with the 55 nm flow film results.And according to the characteristics of the device,a corresponding ESD full chip protection scheme is proposed.It provides a reference for future ESD protection.(2)In 21 nm CMOS processes,the design window of I/O port is determined to be 1.32V-3.7V and the design window of power port is 2.8V-7V.Further,based on the narrow design window,DCSCR,DTSCR and diode-chain are designed to complete full chip ESD protection.Firstly,this article changes the trigger voltage of the DCSCR in a stacking manner so that it can meet different design windows,and the two DCSCRstacked device meet the power port design window and can be used for power port protection;then this article also proposes an improved layout method to reduce the onresistance of DCSCR by 1.5Ω;finally,in order to make the DTSCR turning on easily,the P-well resistance of the DTSCR is increased so that it can be used for I/O port protection.(3)For some advanced bidirectional I/O ports,ESD protection devices are usually required to have dual-directional current conduction capacity.A novel RC-triggered bidirectional ESD protection circuit is proposed to meet the requirement.In this circuit,the improved bridge rectifier circuit is formed by diode rectifier circuit paralleling MOSFET rectifier circuit.The circuit can convert the input voltage in I/O port ranging between negative and positive values into a single polarity input voltage to the RCtriggered circuit and turn on the clamping device NMOS to discharge the ESD current.The novel circuit can provide efficient bidirectional ESD protection for the I/O port when the input voltage in I/O port ranging between negative and positive values by verifying through SPICE simulation software.更多还原