【作者】 杨波；

【导师】 谭克俊；

【作者基本信息】 大连海事大学 ， 电子科学与技术， 2019， 硕士

【摘要】 图像拼接技术指从多个图像中搜集所有的重要信息,并将这些信息拼接到单个图像的过程。作为图像处理技术中的重要研究课题之一,图像拼接技术在遥感图像、医学图像、辅助驾驶等领域都有着很高的实用价值,也得到了广泛的发展和重视。本文研究的图像拼接技术使用的是Zynq可扩展处理器平台,该平台采用了 ARM+FPGA的结构。针对可见光图像的配准与拼接,利用软硬件协同设计的方法,在FPGA端完成图像拼接技术中的图像配准算法及拼接图像的显示;在ARM端完成图像的采集、图形界面、整个系统的控制以及图像的融合拼接;ARM与FPGA通过VDMA来进行数据的交互。这样既能充分利用FPGA的强大的并行性和丰富的逻辑资源,又能利用ARM运行嵌入式系统及处理复杂算法的优势,实现设计的灵活和功耗的降低,提高整个系统的运行速度。本文详细分析了常用的图像配准算法的流程、优点以及适用场景,对各个算法加以对比、分析,并将相位相关法和ORB算法移植到FPGA端进行硬件加速。本设计使用高层次综合工具将图像配准算法移植到FPGA端,相位相关法IP核中包括图像的傅里叶变换、互功率谱计算以及图像的傅里叶反变换;ORB图像配准IP核包括快速角点检测、Harris角点响应以及BRIEF描述子等。通过开发C语言、仿真、优化资源等操作将其综合成RTL级代码封装成图像配准IP核。并利用Vivado将该IP核搭建到硬件电路,实现图像配准的硬件加速。本文还总结了高层次综合开发过程的实践过程及优化方法。本设计在ARM端主要完成两类任务,一方面是根据图像配准IP核的结果对源图像进行融合拼接,另一方面是图像拼接系统的控制,包括图像的采集、待配准图像数据的读写控制、VDMA的配置、图形界面的设计以及图像配准IP核的驱动设计,完成嵌入式Linux系统的移植,实现图像拼接系统的软硬件协同处理。经过实验验证,图像拼接系统能够在Zeboard开发板上很好的运行,实现了界面良好、处理速度高的嵌入式图像拼接系统。更多还原

【Abstract】 Image mosaic technology refers to the process of collecting all important information from multiple images and mosaicing the information into a single image.As one of the important research topics in image processing technology,image mosaic technology has high practical value in remote sensing image,medical image,assisted driving and other fields,and has also been widely developed and valued.The image mosaic technique studied in this paper uses the Zynq scalable processor platform,which uses the structure of ARM+FPGA.For the registration and mosaic of visible light images,the image registration algorithm and the mosaic image display in the image mosaicing technology were completed on the FPGA side by means of software and hardware collaborative design.The image acquisition,graphical interface and the whole system control and mosaicing images were completed on the ARM side.ARM and FPGA used VDMA for data interaction.In this way,the powerful parallelism and rich logic resources of the FPGA can be fully utilized,and the advantages of ARM running the embedded system and processing the complex algorithm can be utilized,the design flexibility and power consumption can be reduced,and the running speed of the whole system can be improved.In this paper,the flow,advantages and applicable scenarios of commonly used image registration algorithms were analyzed in detail.The algorithms were compared and analyzed,and the phase correlation method and ORB algorithm were transplanted to the FPGA for hardware acceleration.This design used a high-level synthesis tool to transplant the image registration algorithm to the FPGA.The phase correlation method IP core included image Fourier transform,cross-power spectrum calculation and inverse Fourier transform of the image.ORB image registration IP core included fast corner detection,Harris corner response and BRIEF descriptors.Through the development of C language,simulation,optimization of resources and other operations,it is integrated into RTL-level code packaged into an image registration IP core.And used Vivado to build the IP core into the hardware circuit to achieve hardware acceleration of image registration.This paper also summarized the practical process and optimization methods of the high-level integrated development process.This design mainly accomplished two types of tasks on the ARM side.On the one hand,it fused the source image according to the result of image registration IP core,and on the other hand it controled the image mosaicing system,including image acquisition and image data to be registered.Reading and writing control,VDMA configuration,graphic interface and the drive design of image registration IP core,the transplantation of embedded Linux system were accomplished in this design and realized the software and hardware co-processing of image mosaicing system.After experimental verification,the image mosaicing system can run well on the Zeboard development board,and realized an embedded image mosaicing system with good interface and high processing speed.更多还原