【作者】 高原；

【导师】 高志强；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2019， 硕士

【摘要】 更快更高效的通信技术带来了更多应用的可能性,让人们的生活越来越便利。随之而来的,由于广泛用于通信本身的收发信号过程和采集生产用于通信的内容的过程中,对高带宽的ADC的需求也相应增加。实际上,除了单纯的对带宽和精度的要求外,兼容多种通信标准不同的精度和带宽的需求也是普遍存在的。跟离散时间sigma-delta ADC相比,连续时间的sigma-delta ADC能实现更高的带宽,更适合于对中高速信号进行处理,同时又对精度有一定要求的场合。通过对sigma-delta ADC中的抽取滤波器进行配置,可以实现不同频率的输出,而且由于前级sigma-delta调制器的特性,对应可以实现不同带宽和精度的输出。这些特点使得可配置的连续时间sigma-delta ADC跟上述需求相契合,作为一种可以兼容包含中高速信号在内的多种通信标准的精度和带宽要求的ADC方案具有相当大的研究价值。本文针对兼容包含中高速信号在内的多种通信标准的精度和带宽的需求,给出了一种可配置的连续时间sigma-delta ADC的设计。调制器部分采用了3阶反馈结构,4位量化的连续时间sigma-delta调制器。对调制器进行了系统级建模,并考虑了其中的积分器和反馈DAC带来的非理想因素。给出了调制器的电路和版图设计,以及后仿真的结果。调制器的版图面积约为1.8×2.0mm~2,调制器在4MHz,1MHz和250kHz带宽下的信噪比分别为74.26dB,101.03dB和107.85dB,谐波失真-118.1dB,对应NBW=5859Hz的噪底约为-140dB。sigma-delta ADC的抽取滤波器部分设计为抽取因子可配置的抽取滤波器。滤波器采用CIC滤波器,CIC补偿滤波器和半带滤波器多级级联的结构,其中CIC滤波器的抽取率可配置。整个抽取滤波器的抽取因子可配置为32,64,128,256和512几档。给出了各级滤波器的系统级设计,具体实现的电路结构以及版图设计。滤波器的通带纹波不超过0.01dB。滤波器的版图面积约为1.8×2.0mm~2,抽取滤波的功能正确。调制器和抽取滤波器两部分组合成可配置的连续时间sigma-delta ADC,后仿真结果表明,在4MHz,1MHz和250kHz带宽下,ADC的信噪比分别为73.68dB,100.12dB和107.09dB,谐波失真约-120dB,对应NBW=5859Hz的噪底约为-140dB。实现了ADC可配置为不同的带宽精度模式,同时可以满足对应的带宽和精度要求。更多还原

【Abstract】 Faster and more efficient communication technologies bring more possibilities for applications and make people’s lives more convenient.Along with this,the demand for high-bandwidth ADCs has increased correspondingly due to the widespread use of the signal-transmission process of the communication itself and the acquisition of content for communication.In fact,in addition to the pure bandwidth and accuracy requirements,the need for compatibility with different communication standards with different accuracy and bandwidth is also ubiquitous.Compared with the discrete-time sigma-delta ADC,the continuous-time sigma-delta ADC can achieve higher bandwidth,and is more suitable for processing medium and high-speed signals,while at the same time requiring accuracy.By configuring the decimation filter in the sigma-delta ADC,the output of different frequencies can be realized,and due to the characteristics of the pre-stage sigma-delta modulator,the output can be realized with different bandwidth and accuracy.These features make configurable continuous-time sigma-delta ADCs compatible with these requirements,and are of considerable value as an ADC solution that is compatible with the accuracy and bandwidth requirements of multiple communication standards including medium to high-speed signals.This paper presents a configurable continuous-time sigma-delta ADC design for the compatibility and bandwidth requirements of various communication standards including medium and high speed signals.The sigma-delta modulator portion of the sigma-delta ADC uses a 3-order feedback structure with a 4-bit quantized continuous-time sigma-delta modulator.The system was modeled at the system level and considered the non-idealities brought about by the integrator and feedback DAC.The circuit and layout design of the modulator,as well as the results of the post simulation,are given.The layout area of the modulator is about 1.8×2.0mm~2,and the signal-to-noise ratio of the modulator at 4MHz,1MHz and 250kHz bandwidth is74.26dB,101.03dB and 107.85dB,and the harmonic distortion is-118.1dB,corresponding to the noise of NBW=5859Hz.The bottom is about-140dB.The decimation filter portion of the sigma-delta ADC is designed as a decimation factor configurable decimation filter.The filter adopts a CIC filter,a CIC compensation filter and a half-band filter in a multi-stage cascade structure,wherein the decimation rate of the CIC filter is configurable.The decimation factor of the entire decimation filter can be configured to be 32,64,128,256,512.The system level design of each level of filter,the circuit structure and the layout design of the specific implementation are given.The passband ripple of the filter does not exceed 0.01 dB.The layout area of the filter is about 1.8×2.0mm~2,and the filtering function is correct.The modulator and decimation filter are combined into a configurable continuous-time sigma-delta ADC.The post-simulation results show that the signal-to-noise ratio of the ADC is 73.68dB,100.12dB and 107.09dB,respectively,at4MHz,1MHz and 250kHz bandwidth.The harmonic distortion is about-120dB,and the noise floor corresponding to NBW=5859Hz is about-140dB.The ADC can be configured to different bandwidth accuracy modes while meeting the corresponding bandwidth and accuracy requirements.更多还原