【作者】 刘勇；

【导师】 周泽坤； 郭向阳；

【作者基本信息】 电子科技大学 ， 工程硕士（专业学位）， 2018， 硕士

【摘要】 通信领域所用到的时钟大多数为锁相环产生的时钟,如在通用串行总线(USB)接口芯片中,数据恢复需要高精度、低抖动的本地时钟,因此锁相环是数据传输系统中数据能够稳定传输的基础。然而为了得到高精度的锁相环输出时钟需要额外的外部时钟晶体来提供参考时钟源。为了节约成本和面积,本论文提出了一款不需要外部参考时钟晶体且稳定输出480MHz的锁相环电路设计与实现,该实现可以应用于USB2.0收发器中。本论文首先对小数分频的原理进行分析,然后结合课题的实际应用,介绍了免外部晶体的方法,即利用USB的通信协议计算出芯片内部的RC时钟频率,再经过小数分频到标准的12MHz作为锁相环的参考时钟,最终达到免外部晶体的目的。然后对锁相环每个模块进行线性化建模,分析其传输特性、稳定特性,并对锁相环中各个模块的噪声传输特性进行分析。小数分频锁相环带来高精度的同时也会产生固定的杂散分量。为了消除杂散分量,本论文提出了使用Sigma-Delta调制方法。首先从量化噪声、过采样技术及噪声整形等基本概念入手,然后介绍Sigma-Delta调制器的原理,最后提出使用MASH1-1-1-1结构的Sigma-Delta调制电路,并且对该调制电路的传输特性进行分析。在电路具体设计方面,对锁相环模拟电路各个模块进行了详细分析。首先介绍了鉴频鉴相器电路中的触发器电路以及通过反馈复位通路上的延时来消除鉴相“死区”;然后分析了基本的电荷泵电路所存在的电荷共享以及电流匹配等问题,提出了消除电荷共享的方法;接下来环路滤波器采用三阶电路来滤除高频噪声,同时通过锁相环开环传递函数确定滤波器的参数值;最后压控振荡器提出一种动态偏置电路和对称负载的延时单元电路来提高抗电源电压和衬底噪声。利用Cadence Spectre工具,在SMIC 55nm的模型库下,进行仿真验证,最后完成版图设计。在版图设计方面,介绍了与版图相关的次级效应,为了节约面积,提出了一种在不增加工艺成本的基础上提高电容值的方法,并给出整体版图布局图。最后,通过对芯片进行测试分析,验证了本论文提出的免外部晶体的小数分频锁相环的可行性。并且该芯片在不同电压与温度条件下测试,结果显示其抖动都在20ps以内,最大功耗低于10.3mW。更多还原

【Abstract】 In the recent decade,most of the clocks in electronic communication field are generated by phase-locked loops(PLLs).For example,the data recovery in universal serial bus(USB)needs local clock with high precision and low jitter.As a result,PLLs are the foundation of accurate and stable data transmission in data transmitting system.However,a high-precision output clock of a PLL requires external crystal oscillator to provide reference clock.In order to save chip area and reduce costs,this thesis presents a design method for a crystal-free 480 MHz PLL which can be applied to USB2.0 transceiver.The thesis consists of the following parts.First,it presents the analysis of the concepts of fractional-N PLLs.Secondly,it describes the way of removing the external crystal oscillator according to real world application,which is to use a 12 MHz reference clock by fractional-dividing calculated internal RC clock frequency through USB communication protocols.Then,a linearized model by linearizing the building blocks of the PLL is proposed to analyse the transfer characteristics,stability and noise transfer characteristics.Fractional-N PLLs bring high precision and also produce a fixed spurious component.A Sigma-Delta modulation fractional-N PLL is presented in this thesis to get rid of the spurious component.Starting with the basic concepts of noise quantizing,oversampling technique and noise shaping,the theory of Sigma-Delta modulation is then described.Finally,it analyses the transfer characteristics of a Sigma-Delta modulation circuit based on MASH 1-1-1-1 structure.Detailed analyses and design procedures of PLL building blocks are presented.The structure of the analyses is composed of the following parts.First,it presents a flip-flop circuit for Phase-frequency Detector(PFD)and a way of minimize the effect of dead-zone by adding delay cells at the feedback reset path.Second,the issue of charge-sharing and current mismatch is analyzed and a way to minimize the charge-sharing effect is proposed.Third,a high frequency noise rejecting third-order loop filter’s component parameters are calculated through PLL’s open loop transfer function.At last,a voltage-controlled oscillator(VCO)is proposed with high supply and substrate noise rejection capability using dynamic biasing circuit and symmetric load Maneatis delay cell.The PLL’s performances are verified and layout drawn using SMIC55 nm process,through Cadence Spectre.In circuit layout perspective,the secondary effects of layouts are presented.For the sake of saving chip area,a method of increasing the capacitance of a capacitor is proposed,which has zero process cost.The total floor plan is also presented.At the end of the thesis,test and analysis are performed to the manufactured chip.The feasibility of a crystal-free Sigma-Delta fractional-N PLL is verified.Under different supply voltage and temperature circumstances,the PLL presents timing jitter less than 20 ps and consumes power less than10.3mW.更多还原