【作者】 张娟；

【导师】 李文渊； 赵文遐；

【作者基本信息】 东南大学 ， 工程硕士（专业学位）， 2018， 硕士

【摘要】 快速发展的计算机技术、数字信号技术以及集成电路等技术,使得对数模转换器(DAC)的性能要求越来越高,DAC连接数字信号和模拟信号,其转换速度已经成为制约整个系统高速发展的瓶颈之一,因此研究设计具有自主知识产权的高速高性能DAC具有十分重要的现实意义和广阔的应用前景。本文采用IBM 0.13μm BiCMOS工艺设计了“4+4”分段式全温度计译码电流舵结构的8位DAC。文章首先阐述了DAC的基本原理、性能参数以及常用基本结构,通过对三种结构的性能进行分析和比较,确定了8位“4+4”分段全温度计译码电流舵结构,这种结构改善了线性度,并且芯片面积较小;其次对影响DAC的相关性能因素进行分析,并得出影响DAC静态和动态性能的主要原因是电流源的匹配误差、电流源的有限输出阻抗大小以及译码方式选择,为后续电路设计提供理论支撑;然后对DAC电路进行系统设计,主要包括数字电路模块和模拟电路模块两个部分。模拟电路部分主要设计带隙基准电压源以及电压转电流偏置电路、电流源栅压产生电路以及电流源级开关管等电路。数字部分主要设计输入寄存器、时钟驱动电路、温度计译码电路以及开关驱动波形产生电路等电路。在电路设计过程中,重点对电流源的设计和开关驱动波形部分进行了性能优化。通过电流源尺寸与精度的关系来确定电流源尺寸,通过采用共源共栅电流源结构来提高电流源输出阻抗,通过采用层次对称开关顺序以减小电流源版图的对称误差以及梯度误差。开关驱动波形电路则通过加入限幅电路输出低摆幅高交叉点信号来减小输出信号毛刺和提高电路速度;最后对整个电路设计进行反复调试、仿真验证。本文完成了DAC芯片的原理图设计、版图设计以及后仿真验证,版图整体面积为775μm×745μm,通过对所设计的DAC电路进行仿真结果表明:该电路最高可在8GHz采样频率下稳定工作,静态特性和动态特性良好。在1.5V电源电压下,功耗为54.79mW,DNL小于0.1LSB,INL小于1LSB,在8GHz时钟采样频率,3.95GHz输出信号频率下,SFDR为37.4dB。本文选用分段式全温度计译码电流舵架构DAC的设计,对今后高速DAC的设计和应用有一定的意义。更多还原

【Abstract】 Rapidly developing technologies such as computers,digital signals,and integrated circuits are increasingly demanding the performance of digital-to-analog converters(DAC).The conversion speed of DAC,which connects digital signals and analog signals,has become one of the bottlenecks restricting the high-speed development of communication system.Therefore,it is of great practical significance and broad application prospects to research and design high-speed DAC with independent intellectual property rights.In this thesis,an 8 bits high speed current steering DAC with “4+4” segmented full thermometer decoding is designed based on IBM 0.13μm BiCMOS process.Firstly,we describe the basic principle,performance parameters,and the common basic structure of DAC.Through the analysis and comparison of the performances of the three structures,the current steering configuration of 8-bit “4+4” segmented full thermometer decoding structure is determined,which combines the advantages of good linearity and small outer part.Secondly,by analyzing factors influencing the performance of DAC,it is concluded that the main factors that affect the static and dynamic performance of DAC are the matching error and the magnitude of finite output impedance in the current source,and the selection of the decoding method,which provides theoretical support for the subsequent-up circuit design.Thirdly,the systematic design of the DAC circuit is carried out,including the design of digital circuit and artificial circuit.The artificial circuit part mainly covers the circuits of band-gap voltage reference,voltage to current bias circuit,current source gate voltage generation circuit,and the current source-level switch tube.While the digital part mainly contains the circuits of input register,clock driver,thermometer decoder,and the switch driving waveform generation circuit.During the process of circuit design,the optimization focuses on the performances of the current source design and the switch driving waveform.The size of the current source is determined by the relations between the size and precision of the current source;the output impedance of the current source is improved by using the common source common gate current source structure;and the gradient error of the current source layout is reduced by adopting the hierarchical symmetrical switch sequence.The switch driving waveform is designed to reduce the output signal burr and increase the speed of the circuit by adding the output of the limiting circuit.Finally,the whole circuit design is debugged and simulated repeatedly.The schematic design,layout design and post-simulation verification of the DAC chip are completed in this thesis,with the overall area of the layout of 775μm×745μm.The simulation of the designed DAC circuit shows that the circuit can work stably at the sampling frequency of 8GHz with good static and dynamic characteristics.Under the 1.5V power supply voltage,the power consumption is 54.79mW;the DNL is less than 0.1LSB;and the INL is less than 1LSB.Under the 8GHz clock sampling frequency and 3.95 GHz output signal frequency,the SFDR is 37.4dB.The current-steering DAC with segmented full thermometer decoding design adopted in this thesis is of great significance to the future design and application of the high speed DAC.更多还原