【作者】 陈正；

【导师】 唐鹤；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2017， 硕士

【摘要】 基带(Baseband)是协助手机完成无线网络建立和通信工作。其功能囊括手机通信的物理层面。基带芯片的功能分为发送和接收。接收端的功能按顺序排列为:接收信号、滤波、模数转换、数字信号处理。目前无线通信设备发展迅速,基带通信的频率越来越高,对模数转换的要求也随之变高。由于SAR ADC具有尺寸小、功耗低等特点,SAR ADC适合集成在基带芯片之中。传统SAR ADC的采用了状态机控制的同步时序逻辑,单通道采样速率难以提升。近年来,随着异步时序逻辑的兴起,异步时序逻辑已经成为一种高速SAR ADC的标准配置。本文基于SMIC 55nm CMOS工艺,设计了一个分辨率为10位,采样率为100Msps的SAR ADC。SAR ADC核心结构包括:采样开关、电容阵列、动态比较器、异步时序逻辑等模块。首先,简单描述了脉冲调制电路、采样开关、异步时序逻辑的结构和设计过程,对于采样开关的要点进行了说明,给出了本次设计中的异步时序逻辑的时序图。然后,详细描述了电容阵列、比较器的设计。其中对电容失配、噪声、功耗都做了详细的仿真和分析。对比较器的失调、噪声做了完整的仿真和说明。并对比较器的比较速度给出了一个较为准确的理论模型。重点描述了失调电压校准电路,首先对比了目前主要的失调电压校准电路,给出了本次设计中失调电压校准电路的结构与工作过程。最后,通过版图仿真分析表明该SAR ADC在100Msps的采样率下能够正常工作。且ADC静态性能优秀,INL和DNL均小于1个LSB。通过仿真得到该ADC动态性能优秀,在输入信号频率为39.4MHz时,其有效位为9.5。最后仿真得到的SAR ADC的功耗为4.4mW,品质因数为60.8fJ/Conv.step。更多还原

【Abstract】 Baseband is a basic module to complete the wireless network in mobile communication.The function of the Baseband chip is divided into sending and receiving.The function of the receiving includes: receiving,filtering,ADC,DSP.With modern wireless communication devices rapidly developed,the frequency of baseband communication is getting higher and higher,and the requirement of ADC becomes tighter.SAR ADC is suitable for integration in baseband chip because of its intrinsic characteristics such as: small size,low power consumption,etc.Traditional SAR ADC sampling rate is difficult to improve because that its timing sequential is controlled by state machine.In recent years,thanks to the invention of asynchronous timing logic module that had become a high-speed SAR ADC standard configuration improve SAR ADC sampling rate.This thesis introduced a 10 Bit 100Msps SAR ADC that based on the SMIC 55 nm CMOS technology.SAR ADC core structure includes: sampling switches,capacitor arrays,dynamic comparator,asynchronous timing logic module,etc.First of all,the structure and design process of pulse modulation circuit,sampling switch,asynchronous timing logic are briefly described.The essentials of the sampling switches and the asynchronous timing logic module are explained.Then,the design of the capacitor arrays and the comparator is described in detail.While the capacitors’ mismatch,noise,power consumptions were completely simulated and calculated,as well as comparator offset,noise.This thesis gives a more accurate theoretical model for the comparison speed of the comparator.In this thesis,I described the offset calibration circuit and compared the mainstream offset calibration structure.Eventually designed an offset calibration circuit module.Finally,the simulation results show that this SAR ADC can work at 100 Msps sampling rate.Static and dynamic performance of this SAR ADC is excellent,all absolute values of INL and DNL are less than one LSB.the ENOB of this ADC is able to achieve 9.5 when the input signal frequency is up to 39.4MHz.The power consumption of this SAR ADC is 4.4mW,the FOM is 60.8fJ/Conv.step更多还原