【作者】 张远；

【导师】 杨军；

【作者基本信息】 东南大学 ， 集成电路设计， 2016， 硕士

【摘要】 传统的嵌入式单线程处理器在管理多路外设的情况下存在中断响应延迟随机,线程切换开销大的问题。硬件多线程处理器通过多个硬件线程并行执行,缩短了中断响应的时间,减小了线程切换开销,在多外设管理上具有明显的优势。缓存(Cache)作为高速存储器具有软件透明,平均性能好的优点,适用于硬件多线程下的多任务并行处理应用场景。而通过动态缓存分区方法可以抑制硬件多线程处理器下不同硬件线程对一级共享Cache访问产生的相互污染,提升系统整体性能。目前,适用于多级Cache结构的最近未使用(Not Recently Used, NRU)动态缓存分区方法在硬件多线程处理器的一级Cache下存在命中估计不准确,划分方式复杂且无法抑制不恰当划分这两方面问题。命中估计不准确导致硬件多线程处理器的执行效率降低,Cache的不恰当划分影响线程获得的处理器时间片。针对这两个问题,本文设计了一种改进的动态Cache分区方法,对命中估计方法和Cache划分方法进行改进。改进的命中统计分析方法采用一种基于二叉树替换策略的命中位置估计方式,该命中位置估计方式通过对二叉树状态值进行简单逻辑运算得到命中位置信息,在提高命中估计精度的同时降低硬件实现复杂度。结合该命中统计分析方法和硬件多线程处理器的特点,改进的Cache分区方法采用了一种低硬件开销的非遍历划分算法来降低划分计算时间复杂度,并通过将Cache分为可划分区域和不可划分区域的部分分区方式来抑制不恰当划分产生的后果,最终实现在不降低干扰消除能力的情况下提升硬件多线程处理器系统的性能。经Mibench测试表明,在4线程并行执行的情况下,本文设计并实现的改进动态Cache分区方法将干扰缺失数量占总缺失数量的比例从50%降到了15%,每时钟周期执行指令数(Instruction Per Clock, IPC)吞吐率和加权加速比相对于NRU替换策略的动态缓存分区方法分别提高了11.8%和15%。更多还原

【Abstract】 The traditional single-threaded embedded processor had the problems of random interrupt response latency and thread switching overhead under the management of multiple peripherals. Hardware multi-thread processor reduced the interrupt response latency and the thread switching overhead, due to the multiple hardware threads parallel executioa As the high speed memory, Cache has the advantages of software transparent and good average performance. The dynamic Cache partitioning method could promote system performance by suppressing the cross contamination of different hardware threads accessing the first level shard Cache.The pseudo LRU dynamic Cache partitioning method, for multi-level Cache structure, has the problems of complex partitioning and unable to suppress inappropriate partitioning in the first level Cache of hardware multi-thread processor. Complex partitioning could reduce the processor’s execution efficiency and the processor time slice could be affected by inappropriate partitioning. The optimized dynamic Cache partitioning method was involved to solve those problems. Hit statistical analysis, based on binary tree replacement strategy was used in analysis circuit To reduce the partitioning complexity, the non-ergodic partitioning algorithm of low hardware overhead was adopted in analysis circuit and to suppress the inappropriate partitioning by partial partitioning method. The performance of system was improved eventually without reducing the reducing the interference elimination capability.The Mibench test shows that, by using the optimized dynamic Cache partitioning method in case of 4 threads executing in parallel, the interference miss rate was reduced from 50% to 15% and the IPC throughput rate and weighted speedup rate, compared to dynamic partitioning based on NRU replacement strategy, was increased by 11.8% and 15%respectively.更多还原