【作者】 金毅；

【导师】 施国勇；

【作者基本信息】 上海交通大学 ， 软件工程， 2007， 硕士

【摘要】 随着SoC设计中工艺特征尺寸的减小,工作频率的提高,供电电压的下降,功率密度急剧增大。在90nm及以下的SoC设计中,功耗和压降成为不可忽略的参数指标。因此,电源完整性分析成了流片前签核阶段的必要工作。并且,单纯的静态压降分析已经不足以发现并解决由压降过大引起的潜在问题,动态压降分析更加必要,也更为重要和复杂。本文将以CMOS90GP工艺的CPU设计项目为例,介绍SoC的动静态压降的分析方法。为了满足CPU 1GHz以上工作频率的需要,供电电压选择了90GP工艺中较高的供电电压1.2V。更多还原

【Abstract】 With the continuous shrinking of process technology, higher frequency and lower supply voltage in SoC design, power density increases sharply. For the SoC design in 90nm and beyond, power consumption and voltage drop become very important parameters. In this trend, power integrity analysis is becoming a necessary task in signoff stage before chip tape-out. Moreover, static voltage drop analysis only is not enough to find and solve all the potential problems brought by large voltage drop. It is necessary to do dynamic voltage drop analysis, which is a more important and complex task. In this paper, we use an example of CPU design in CMOS090 technology to introduce the method of static and dynamic voltage drop analysis. In order to meet the requirement of 1GHz frequency in CPU, a supply voltage of 1.2V is chosen.更多还原