节点文献
码率可控的JPEG-LS近无损图像压缩编码器硬件实现
Hardware Implementation of Rate Controlled JPEG-LS Near Lossless Image Compression Encoder
【作者】 张毅；
【导师】 李云松；
【作者基本信息】 西安电子科技大学 ， 通信与信息系统， 2014， 硕士
【摘要】 随着计算机通信技术的迅速发展，特别是多媒体技术的广泛运用，数字图像的分辨率越来越高，图像传输的数据量越来越大。庞大的数据量给图像的传输和存储带来巨大的压力，因此高效的图像压缩编码技术在图像通信系统中扮演着越来越重要的角色。JPEG-LS是在ISO/ITU标准中用于对静态连续色调图像进行无损和近无损压缩的一种算法。该算法性能优越，复杂度低，可广泛的应用于无损/近无损图像压缩任务中。但是JPEG-LS存在一个缺陷：即输出码率变化较大而且不可控制，这个缺点严重限制了JPEG-LS的应用。因此，需要设计一种码率可控的JPEG-LS编码器来应对一些带宽受限环境下的图像压缩任务。本文结合JPEG-LS算法标准和FPGA硬件平台的特点，提出了一种新的JPEG-LS码率控制算法，与现有技术相比，具有码率控制精度高，码率收敛速度快等优点。在此基础上，使用Verilog硬件描述语言在FPGA硬件平台上实现了码率可控的JPEG-LS近无损图像压缩编码器，与已有的硬件结构相比，该编码器编码效率高，系统功耗低，且不需要片外存储器来缓存图像。
【Abstract】 With the rapid development of computer communication technology, especiallythe widespread use of multimedia technology, the resolusion of digital image becomeshigher and the amount of data involved in image transmission becomes larger. Thehuge amount of data put tremendous pressure on the transmission and storage ofimages, so efficient image compression technology plays an increasingly importantrole in the image communication systems.Proposed by ISO/ITU, JPEG-LS is the new standard for lossless and near losslesscompression of continuous-tone still images. With its superior performance and lowcomplexity, JPEG-LS can be widely used in lossless and near lossless imagecompression tasks. But there is a flaw in JPEG-LS: the output rate changes largely andis uncontrollable, this shortcoming severely limits the application of JPEG-LS.Therefore, rate controlled JPEG-LS encoder is needed to accomplish the imagecompression tasks under limit band-width environment.In this paper, based on the characteristic of the JPEG-LS algorithm and the FPGAhardware platform, we proposed a new rate control algorithm for JPEG-LS. The newbit-rate control algorithm proposed in this paper is superior to the existing technologyon the accuracy of bit-rate and the speed of bit-rate convergence. On this basis, weimplement the rate-controlled JPEG-LS near lossless image compression encoder onthe FPGA platform using Verilog hardware description language. Compared with thepublished architectures, the proposed encoder has a high efficience in encoding withlow power consumption, and does not need memory chip to cash the images.