【作者】 刘勇；

【导师】 刘鹏；

【作者基本信息】 浙江大学 ， 电子与通信工程（专业学位）， 2013， 硕士

【摘要】 生产工艺的不断进步以及新兴应用程序的要求不断驱动着处理器性能的飞速提升。然而嵌入式处理器面临着新的挑战：一方面,存储器与处理器的性能差距不断制约着处理器的整体系统性能；另一方面,大量新应用的高精度浮点要求对处理器设计提出了新的需求。本文通过分析应用特性,采用数据预取优化处理器存储系统,并设计浮点单元加速处理器数据处理。主流的预取机制设计和配置并不适用嵌入式处理器：过于激进的预取策略会干扰处理器正常访存行为；复杂的预测和控制机制会消耗大量功耗和面积。本文设计了一种基于流信息表的可变步长流预取机制。通过优化的最小差值法对数据流进行判定和过滤,降低电路设计复杂度；同时通过设置预取缓冲降低高速缓存(cache)端口冲突率；并对预取数据采用单独的cache替换策略,弥补因为cache的污染对预取效果造成的负面影响。NoCOP硬件模拟平台仿真结果显示,针对EEMBC和SPEC2006测试集,本文的流预取机制相较于无预取时,平均性能提升比例为4.3%,性能最大提升16%；相较于MSP (minimum delta prefetching)机制,平均性能提升10.5%；面积增加3.5万等效门,总功耗增加30.1mW。目前大多数预取机制并不能同时兼顾流式和链式数据结构,且已有的链式预取机制存在着存储空间开销大或预取准确度低的问题。本文设计了集成流预取引擎和指针预取引擎的自适应多模式预取系统,根据处理器实时运行信息判断当前工作模式效率,并完成在流预取、指针预取和无预取二种模式下的切换调整。其中,我们设计的FCDP(filtered content directed prefetching)指针预取机制,通过基于偏移地址的过滤方法对CDP(content directed prefetching)机制进行准确率的优化,可以平均降低35%的预取发起数量。NoCOP硬件模拟平台仿真结果显示,针对EEMBC、SPEC2006和Olden测试集,预取系统与单独采用流预取和FCDP预取时分别提升11.7%和50.6%,能在预取效果不理想时及时关闭预取引擎,降低系统功耗。根据新应用大量的浮点数据,以及越来越高的精度要求,本文设计了适用于嵌入式处理器的浮点单元,用于加速浮点数据的处理。同时,提出了利用软件模拟器统计应用特性来指导RTL(register transfer level)级设计的方法实例。浮点单元设计采用load/store与浮点算术指令分开处理的方式,高度复用了原整型流水线的逻辑单元,并与整型流水线紧密耦合。实验与逻辑综合结果表明,浮点单元支持MIPS32单精度浮点指令集；在worst case下最大工作频率为495MHz,在typical case下最大工作频率为794MHz；面积增加24.8万等效门,功耗为88.3mW。更多还原

【Abstract】 The improvement of processing technology and the requirement of new application promote the rapid increase in processor performance. However, embedded processor faces new challenges:on one hand, the performance gap between memory and processor restricts the performance of processor system; on the other hand, a large number of high-precision floating-point applications ask for new design requirement. After the analysis of application characteristics, we optimize the memory sub-system by data prefetching, and design a floating-point unit to accelerate the data processing.The design and configuration of mainstream data prefetching mechanism does not apply to embedded processors:an overly aggressive prefetching strategy will interfere the normal memory accesses; and complex prediction and control mechanism will consume a lot of power and area. This thesis proposes a filtered stream prefetcher with non-unit strides for embedded processors. We allocate and filter the data stream by optimized minimum delta algorithm to reduce the complexity of circuit design; and set a prefetch buffer to reduce the collision rate of cache ports; and optimize the cache replacement policy to make up the negative impact caused by cache pollution. The emulation result on NoCOP platform shows that, for EEMBC and SPEC2006benchmark sets, the speedup is4.3%in average and16%in maximum compared to no prefetching, and10.5%compared to MSP(minimum delta prefetching) mechanism. The increasing area is about35,000gates, and increasing power is30.1mW.Most prefetching mechanism cannot prefetch both stream and linked data structure, and there is large storage consumption or low prefetching accuracy in current pointer prefetching mechanisms. This thesis proposes an adaptive muti-mode prefetching system, which integrates stream prefetcher and pointer prefetcher. The prefetching system can adaptively switch the prefetching mode among stream prefetching, pointer prefetching and non-prefetching, according to processor run-time information. The FCDP(filtered content directed prefetching) can reduce35%prefetching requests in average compared to CDP(content directed prefetching), by using a filtering method based on load offset address. The emulation result on NoCOP platform shows that, for EEMBC, SPEC2006and Olden benchmark sets, the speedup of multi-mode prefetching system is11.7%compared to stream prefetching mode, and50.6%compared to FCDP mode. The system can shut down to reduce power consumption when prefetchers are not efficient.According to the case that more and higher precision floating-point data in current applications, a floating-point unit is designed for embedded processor to accelerate the data processing. We statistic the application characteristics by software simulator to guide the RTL-level(register transfer level) design. The design of floating-point unit handled the load/store and arithmetic instructions separately. The floating-point unit highly reuses the logic unit of integer pipeline, and tightly coupled with integer pipeline. The simulation and logic synthesis result shows that the floating-point unit fully supports MIPS32single-precision floating-point instruction set. The maximum frequency is495MHz in worst case and794MHz in typical case. The increasing area is about248,000gates, and increasing power is88.3mW.更多还原