节点文献
基于MicroBlaze的PCIe协议适应层设计
Design of the PCIe Protocol Adaptation Layers Based on MicroBlaze
【作者】 宋哲；
【导师】 马建国；
【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2012， 硕士
【摘要】 在计算机和工业系统中，设备之间经常需要进行高速的数据交换，随着数据传输速率的提高，设备之间进行数据传输存在的最大的问题是数据按照某种协议进行传输后造成时钟不同步，进而导致数据的丢失，当传输速率达到Gbps时这一问题更加严重。解决这一问题的关键技术是在设备间添加一个可以硬件实现的协议适应层。协议适应层（Protocol Adaptation Layers，PAL）是WiGig联盟定义的、在60GHz频段上支持特定数据和显示的协议标准。PAL不仅支持音视频接口，如HDMI和DisplayPort，还支持通用I/O，如USB和PCIe，并且允许这些标准的接口以无线传输的方式直接访问Mac层和物理层。相比于其他通过软件实现的协议，PAL可以在硬件中开发和实现，从而可以最大化的提高性能和降低功耗。从WiGig的定义上看，PAL既支持PCIe接口，也提供对USB3.0接口的支持，但是目前Xilinx公司所提供的FPGA开发板尚未提供对USB3.0的支持，因此，本文针对PCIe接口的PAL进行了设计和开发。本文基于Xilinx Virtex-6FPGA搭建PCIe接口的PAL硬件平台，PC端驱动将数据通过PCIe接口传输到FPGA上，MicroBlaze软核处理器调用AXI4总线对数据进行接收和处理，处理后的数据经过GTX高速收发器传输到下一级FPGA中。经过规范化CSP语言对整个系统模型的验证和优化后，本文所搭建的PAL平台在Xilinx ML605开发板上进行了测试，PC端传输数据到FPGA上的速度可达6.4Gbps，FPGA之间数据的传输速度可达3.2Gbps。
【Abstract】 In the computer and industrial systems, high-speed data exchange within devicesis often occurred. With the increasing of a data transmission rate, the issue is thattransmitting data as some protocol causes the asynchronization, which results in theloss of data. The situation is even more serious when the transmission rate is up toGbps. The key to solve this problem is to add a protocol adaptation layer which canbe implemented in hardware.The WiGig Alliance defines Protocol Adaptation Layers (PAL) that supportspecific data and display standards over60GHz. The initial PAL are audio-visual(A/V), which defines support for HDMI and DisplayPort, and input-output (I/O),which defines support for USB and PCIe. PAL enables highly efficientimplementations because they are defined directly on the WiGig MAC and PHY,rather than layered on other protocols and can be implemented in hardware. Thismaximizes performance and reduces power consumption.The WiGig Definitions of PAL exist for USB3.0and PCIe. However, there areno Xilinx development boards for USB3.0. Therefore, this paper focuses on PCIe.The PCIe PAL hardware platform is created based on the Xilinx Virtex-6FPGA. First,the PC driver feeds the data into FPGA via PCIe. Then, the received data are flowedinto AXI4and processed by MicroBlaze soft-processor. After that, the processed dataare transmitted to the next level FPGA via GTX high-speed transceiver. Afterverification and optimization of the entire system using CSP formal language, thePAL platform is tested on the Xilinx ML605development board. The data rate fromPC to FPGA is up to6.4Gbps and the data rate between two FPGAs is up to3.2Gbps.