【作者】 孙涛；

【导师】 王国兴； 汪宁；

【作者基本信息】 上海交通大学 ， 集成电路工程， 2013， 硕士

【摘要】 模数转换器在现代的电路系统中广泛应用，典型的应用包括无线收发机和CMOS图像传感器等。随着各种新的发展趋势以及不断增长的无线数字通信市场，更高采样速率、更低功耗以及更好线性度的模数转换器的需求越来越大。得益于半导体工艺尺寸的缩小，数字集成电路可以获得更丰富的功能和性能，然而对于模拟集成电路来说，更小的工艺尺寸以及更小的供电电压意味着想要保证相同的信噪比必须降低噪声，对于采样电路来说需要采用更大的采样电容，这就需要更大的电流来驱动，从而使得系统的功耗增加。功耗对于很多要求移动性能的系统来说是需要特别考虑的指标，如何降低模拟电路的功耗成为热门研究课题。本论文主要研究用于ISM频带收发机中的流水线模数转换器的低功耗设计与实现。主要采用的低功耗技术包括：前端无采样保持电路设计、电容按比例缩小设计、动态比较器设计、动态功耗调整设计等。在本论文中，设计了一个10比特20兆采样速率的流水线模数转换器，最低功耗约为5毫瓦，芯片测试得到有效位数为8.53比特，动态范围为55.12dB，无杂散动态范围为59.19dB，信号与噪声及总谐波失真比为53.13dB，总谐波失真为57.49dB。更多还原

【Abstract】 Analog-to-digital converters have been widely used in modern circuitand systems including wireless transceivers, CMOS image sensors and soon. Along with the new trends and continuous growth in wirelesscommunication market, converters with higher linearity, lower power andhigher sampling rate are in great demand.Digital integrated circuits have benefited a lot from the scaling ofsemiconductor feature size, more and more complicated and highperformance digital integrated circuits has been developed. However, dueto the scaling of supply voltage, the signal to noise ratio of analog circuitswould decrease. In order to maintain the SNR, larger sampling capacitorsshould be used. With a larger capacitor the current need to be increased todrive the capacitor which results in a higher system power consumption.This paper mainly focuses on low power design techniques of apipeline ADC. Non-idealities are carefully considered and techniques suchas sampling stage elimination, capacitor scaling, dynamic powerconsumption and dynamic comparators etc. are used.According to the dynamic test of the10bit20Msps pipeline ADC chip,we got an ENOB of8.53bits. The SNR, SFDR, SNDR and THD are55.12dB,59.19dB,53.13dB and57.49dB respectively.更多还原