【作者】 刘博；

【导师】 靖固；

【作者基本信息】 哈尔滨理工大学 ， 计算机系统结构， 2011， 硕士

【摘要】 在半导体工艺和集成电路制造技术飞速发展的今天,系统芯片SoC(system on chip)的设计已成为国际超大规模集成电路的发展趋势和集成电路设计的主流。数量繁多的复合模块集成在一个芯片上,并能够完成更加复杂的工作。鉴于市场日益紧迫的需求,芯片的设计周期愈发变得短暂,因此,SoC芯片中大量地采用了预先设计好的、完整的IP(intellectual property)模块来减少生产时间。但随之也带来了问题,因其规模的庞大,芯片的制造故障随之提高了。这样以来就对芯片的测试提出了更高的要求,不但需要更加精准的时序控制,还需要更长的芯片测试时间,这些都会导致测试成本的提高。测试数据压缩是解决SoC测试成本等诸多问题的一种行之有效的办法,它能够减少测试所需的存储测试数据量,减少测试时间。为了有效地测试SoC,各IP供应商在提供IP核的同时会提供测试向量。一般来说平均每个SoC芯片上就拥有数百亿位的测试向量。通过测试向量的压缩(编码)之后,测试数据量可以缩小20倍以上。本文在深入研究各种测试压缩技术的基础上,着重研究几种用编码方式压缩测试向量的方法,从压缩率和解码电路规模角度上对它们做出比较,得出了使用Golomb编码来进行测试向量压缩是一种简单而又行之有效的办法。Golomb编码最大的特点就是选择了变长到变长的编码方式,这样编码方式灵活,且会使代码字的长度降低。同时,针对Golomb编码中游程长度游离分散不易进行编码压缩的特点,提出了基于分组频率的Golomb码压缩方法,并以公认的ISCAS85基准测试电路中的C17逻辑电路为被测电路进行实验,将编码后的测试向量输入到设计好的解码电路部分,再由该解码器释放出原来的测试向量,最后施加到C17上电路完成全部测试。使用此方案在标准测试电路上的实验,从仿真的实际测试结果看,测试系统的软硬件设计达到了预定的设计目标,各项指标均符合SoC测试的各项要求。在解压电路略微增加的少量代价下测试向量的压缩有了更好的压缩率,从而降低了测试成本。只要加以改进,就可以达到实用化的程度。更多还原

【Abstract】 With the rapid development of semiconductor technology and integrated circuit fabrication technology , the appearance of system chip SoC (system on chip) becomes the mainstream of and occupy the development stage a large scale integrated circuit .Many composite modules are integrated on a single chip, and will be able to accomplish more complex tasks. On the other hand, because the market increase urgently for the demand of the chip design cycle, so that the model of SoC chip massively adopted pre-designed and integrated IP (intellectual property) module to reduce production time. But following gives rise to the question, because its scale is huge so that chip manufacturing fault increased subsequently.Therefore,the test chip put forward higher request. Not only need to be more precise control sequence, but also need longer microchip testing time, these will lead to increase the cost of test. Test data compression is a method that it can solve such problems of SoC testing cost, it can reduce the required test storage test data quantity, reduce test time. In order to test the convenience and integrity, each IP core producers in the supply of IP core will also additional supply the chip test vectors. In general average SoC chip has tens of billions of bit of test vectors. Testing data quantity can reduce to above 20 times after testing the vector compression.On the basis of depth study about various testing compression technology, this thesis focus on researching several methods which encoding compression test vector method.Comparing with them from compression ratio and decoder circuit scale angle, it is concluded that Golomb is a simple and effective method that can code to test vector compression. The biggest characteristic of Golomb code is to choose the length to variable-length coding method, which can reduce code word length of growth rate. At the same time, aiming at the characteristics of Golomb coding run-length coding length disperse and not free compressed, propose a method that based on group frequency Golomb code compression method, and use ISCAS85 benchmark recognized in the circuit C17 logic circuit for circuit under test conducted experiments that converts coded after testing vector input to design good decoder circuit of, then they can release the original test vectors by the decoder.Finally, circuit finish all the test by exert test vector on C17.This scheme experiment on benchmark cicuit, from the simulation of the actual test results look, the software and hardware design of test system achieved the design goal, and each index all conform to the requirements of SoC test. In a small increase in the amount of unzip circuit under test vector compression price have a better compression ratio, which reduces the test cost. We could achieve practical level as long as we improve them.更多还原