【作者】 潘勇；

【导师】 宋刚； 栗华；

【作者基本信息】 山东大学 ， 集成电路设计， 2011， 硕士

【摘要】 随着集成电路设计水平的提高和微电子工艺技术的发展,单个芯片上集成的电路越来越复杂,集成电路(IC, integrated circuit)朝着SoC (System-on-Chip,片上系统)发展的趋势也越来越明显。系统芯片集成技术可以有效地降低芯片系统的功耗、减小芯片的体积、增加系统的功能、提高芯片设计的速度。因此,基于IP(Intellectual Property,知识产权)核的SoC设计方法已经成为当前电路设计的主要设计方法之一。超高频RFID读写器以读写距离比较远、传输速度高和工作稳定等优点一经推出便迅速占领了无线设备尤其是手持设备领域的主导地位。伴随着超高频(UHF)读写器的大范围运用和不断改进创新,把读写器的部分功能尤其是易于实现的数字基带信号处理部分集成到单个SoC系统中将成为一种潮流。因此,本课题的选取具有较大的现实意义。本课题设计了一种带有读写器数字基带信号协议处理单元的片上系统,采用了OpenCores组织维护和提供的开源IP核,包括OR1200 IP核,UART 16550 IP核,GPIO IP核和Wishbone Conmax总线IP核。此外,超高频RFID读写器的协议处理单元IP核由课题组开发,片上RAM IP核,PLLIP核由Altera公司IP核生成工具MegaWizard生成。为了与OpenCores组织提供的开源IP核兼容,本课题所设计的IP核都配置了Conmax标准接口,并通过自顶而下的层次化设计方法,在完成各个IP核的设计与功能仿真后,使各IP核互联形成一个完整的读写器SoC系统。最后,搭建软硬件开发环境完成了对整个读写器SoC系统的验证。本论文对软硬件验证平台、IP模块功能仿真验证、读写器SoC整体系统验证和FPGA验证的实现进行了详细的设计,并给出了模块综合图和仿真波形。更多还原

【Abstract】 With the elevated levels of IC (integrated circuit) design and the development of microelectronics techniques, single-chip integrated circuits are getting more and more complexity, integrated circuit towords SoC (System-on-Chip) developing has become increasingly evident trend. System chip integration technology can effectively reduce power consumption, decrease chip size, increase system functionality, and improve the speed of chip design. Terefore, the SoC design method based on IP (Intellectual Property) core has become one of the main means in the modern IC design.Because of writing and reading further, higher transmission speed and stability of work, when UHF reader appears, it holds wireless filed especially the filed of handheld wireless. With the wide range using and innovation, a part of the reader especially digital basehand signal processing units are integrated into SoC system will be popular.Therefore, the selection of this topic possesses great practical significance.The thesis designs a single chip system with interrogator IP core and uses the IP cores which provided by OpenCores.These include OR1200, GPIO, UART 16550 and Wishbone Conmax Bus IP core and so on. In addition, our group provides the UHF RFID interrogator IP core, simultaneously, Altera supplys the chip RAM IP core and the PLL IP core. In order to keep compatibility with the IP cores which the OpenCores provides, all of them are designed with Conmax interface, and through the top-down hierarchical layout method to enable the IP cores forming a complete SoC system after completing each IP core design and simulation. Finally, I build hardware and software environment to finish the test of the interrogator SoC system.In this paper, I give the detail design including Hardware and Software verification platform, IP module function simulation,the whole SoC simulation and verification, and FPGA verification, at last, provid synthesis map and simulation waveform for the Interrogator SoC system.更多还原