【作者】 郭文平；

【导师】 刘政林；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 非对称密钥算法被广泛应用于数据加密和数字签名等领域,而在众多非对称密钥算法中,RSA是目前公认的最为成熟和完善的算法。但因其算法的复杂性,硬件实现开销一直较大,无法满足嵌入式系统这类资源受限环境应用中对成本与功耗的要求。针对此,本论文设计了一种应用于资源受限环境下的小面积RSA硬件加密引擎,并予以ASIC实现。本论文首先深入分析了RSA的各种实现算法,比较了它们在面积、性能上的优劣,进而在兼顾实现面积和加密速度的原则下采用改进的基2 Montgomery模乘算法和“平方-和-乘”算法作为模乘和模幂的实现算法,设计并实现了RSA硬件加密引擎。在加密引擎的设计中,提出采用256位数据宽度处理的方式代替传统的1024位数据宽度处理,通过折叠数据通道,精简电路结构,并使用片内SRAM,减小实现面积;另外,将RSA核心模块中的4输入加法运算,用优化的进位保存加法器实现,通过优化关键路径延迟,提高最高工作频率。本论文实现了小面积RSA的VLSI设计,使用EDA工具进行了逻辑仿真,FPGA验证和综合,采用HHNEC 0.25um CMOS标准单元库完成版图设计,并成功流片。分析结果表明,1024位密钥长度的RSA硬件加密引擎,整个设计的规模约为24K等效门,最大工作频率为100MHz,处理一组1024位的数据加解密需时275ms。相比于实用芯片西门子SLE66CX160S,本实现面积缩小了55.63%,达到了实用芯片的应用水平。更多还原

【Abstract】 RSA is recognized as one of the most widely preferred algorithms used inasymmetric-key cryptography, which is widely used in data encryption and digitalsignature authentication. However, because of the complexity algorithm, the hardwareimplementation has such a large overhead that it is not suitable in resource-constrainedsystems applications. In order to solve this problem, VLSI implementation of anarea_optimized RSA encryption engine is developed to meet the practical application ofthe RSAalgorithm for hardware implementation.The author analyses firstly some algorithms for RSA implementation, secondly, bycomparing them, chooses modified radix-2 version Montgomery algorithm and R-Lalgorithm to calculate modular multiplication and modular exponentiation. Then,considering the trade off among speed, chip area and flexibility, a RSA encryption enginebased on 256bits data width process is designed, which greatly reduces the area of RSA;in addition, CSA and CLA was used to implement a 4 input adder, which also increasesthe maximum operating frequency, speeds up the computation speed.In this dissertation, the RSA encryption engine has been implemented and sign-offsuccessfully. Simulation and verification results show that the encryption and decryptionof the encryption engine functions correctly; the synthesis results show that besides thebasic function implementation, the improved RSA design introduced an area reduction of55.63% compared with the SLE66CX160S of Siemens, it has 24K gates count with amaximum clock frequency 100MHz, meets the design requirements.更多还原