超高频RFID系统Capture效应下防碰撞算法研究及读写器码元同步器设计

【作者】 李波；

【导师】 王俊宇；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2010， 硕士

【摘要】 超高频无源RFID(Raido Frequency Identification)系统由于具有标签成本低、读写距离远、识别速度快等优点,在物流、零售等领域发展迅速,应用前景广阔。本文的研究内容是基于ISO18000-6C协议的超高频RFID系统中的两个关键技术Capture效应下的多标签防碰撞算法研究、读写器数字接收机中码元同步器设计。Capture效应普遍存在于超高频无源RFID系统中,它通过将碰撞时隙转化为成功时隙从而提高了系统吞吐率。针对目前国内外对Capture效应的分析和建模尚不完善的问题,论文对Capture效应进行了理论建模,并通过蒙特卡罗仿真分析了各因素对Capture效应的影响,然后通过实际仓储环境下的测试验证了模型的准确性,测试结果表明,实测数据与模型仿真值的均方误差小于3%,相对传统模型(均方误差大于12%)有较大幅度的改善；继而以Capture效应为出发点,设计了新的标签估算算法及最佳帧长确定方法,在此基础上对随机型多标签防碰撞算法进行了改进,算法仿真结果表明,在Capture效应下,改进后的防碰撞算法可以使系统吞吐率提升至接近50%；最后对Capture效应下随机型防碰撞算法的系统性能极限进行了理论推导,结果表明,该极限由平均Capture概率决定。相比于防碰撞算法是从MAC(介质访问控制)层入手来改善系统性能,高性能码元同步器设计则是物理层的手段。码元同步器是读写器数字接收机的一部分,数字接收机的主要任务是进行ADC后信号的码元数据率及相位同步、解调及解码,并提供对多数据率的支持,并兼容FMO/Miller编码方式。由于ISO 18000-6C允许标签返回数据率可以存在最大22%的偏差,因此码元频率及相位同步成为数字接收机设计的主要难点。传统的码元同步器多采用基于相关器的架构,其结构简单容易设计并实现,但资源消耗较大、同步精度有限。本文采用基于内插及数字PLL的码元同步器结构,很好地解决了上述问题。仿真结果表明,该结构比相关型码元同步结构(以采用12组相关器为例),数字接收机的PER性能更好,而且资源消耗是相关型码元同步器的50%以下。更多还原

【Abstract】 In this thesis, two of the key techniques in passive UHF RFID systems based on ISO18000-6C standard are studied. One is the analysis and design of multi-tag anti-collision algorithm considering capture effect, the other is the all-digitial symbol synchronizer design of passive UHF RFID reader.Capture effect is ubiquitous in passive UHF RFID systems. By transforming collided slots to successfully identified slots, Capture effect can remarkablely improve the system throughput and therefore becomes a research focus in this area currently. In this thesis, a novel Capture model for passive UHF RFID systems is firstly presented, which considers the characteristics of RFID reader, indoor radio channel, backscattering and spatial distribution of passive tags. Experimental results measured at a warehouse show that the presented Capture model is more accurate than exsiting ones. Based on Capture effect, a novel anti-collision algorithm is then developed, showing a performance improvement than traditional ones. Also, the performance limit of Aloha-based anti-collision algorithms under Capture effect is theoretically derived.Compared with anti-collision algorithm design, which is a MAC (Medium Access Control) layer method to improve system performance, symbol synchronizer design is a physical layer approach to achieve better performance. Symbol synchronizer is part of reader digital receiver, which is responsible for symbol rate and phase synchronization, demodulation, decoding for 40KHz-640KHz FMO/Miller signal. Due to±22% data rate drift of tag backscattering signal, the symbol synchronizer design is the most difficult in digital receiver design. Traditional symbol synchronizers are mostly based on Correlator, and have disadvantages of large resource consumption and low accuracy of symbol synchronization. In this thesis, we present a symbol synchronizer based on digital PLL and interpolation, which avoids the disadvantages mentioned above. Simulation results show the digital receiver equipped with this DPLL-based symbol synchronizer outperforms existing works in SNR-BER performance and resource consumption.更多还原