【作者】 高飞；

【导师】 来逢昌；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2010， 硕士

【摘要】 DDR2 SDRAM是由JEDEC(电子设备工程联合委员会)进行开发的新生代内存技术标准。由于DDR2 SDRAM中数据为双倍传输,即在数据时钟的上升沿和下降沿都同时进行采样操作,因此在DDR2 SDRAM控制器物理层中如何快速准确定位采样时钟就至关重要,能否正确接收和采样数据成为影响内存控制器性能的重要因素。延迟锁相环DLL具备时钟定位准确、抗抖动能力强、锁定速度快等优点,在各种时序系统中得到了广泛的应用。随着内存技术的发展,内存控制器对时钟的抖动和偏差提出了更高的要求,使得DLL在DDR控制器的应用领域得到了越来越重要的重视,并且已广泛应用于高速存储器接口的时钟同步、倍频和多相时钟发生器等电路中。本文通过对DDR2控制器和DLL理论的研究,基于0.13um CMOS工艺,全定制设计了一款应用于DDR2控制器物理层的主从结构的延迟锁相环,工作频率在400MHz,实现了4相的压控延迟线,产生4相延迟时钟。延迟锁相环所产生的延迟时钟保证DDR2在读数据时,数据经过传输线传输后能被正确的采样;写数据时, DLL产生的时钟能精准地控制倍率转化。设计中采用了电荷泵结构的延迟锁相环和差分压控延迟线,改善了压控延迟线的性能。仿真结果表明设计功能正确,性能良好,很好的满足了DDR2控制器物理层对时钟的要求。并且在设计中加入了微调控制以及相对应的测试模块,方便电路的调整和后续测试。同时,主从延迟锁相环采用了较多相同的结构,减少了设计复杂度,减少了芯片面积,易于集成。更多还原

【Abstract】 Delay-Locked Loop clock, with the advantages of accurate clock positioning, anti-shake capability and quick locking ability, has been widely used in a variety of timing systems. With the development of memory technology, there have been more strict demands of clock jitter and bias for the memory controller, which also gives the DLL a more and more important position in DDR controller application fields, and makes DLL widely used in clock synchronization, harmonic and multi-phase clock generator and other circuits for high-speed memory interfaces.Based on the theoretical study of DDR2 controller and DLL, this essay describes the design and implementation of a Master and Slaver of Delay-Locked Loop applied for the DDR2 controller. The DLL works at the frequency of 400MHz, with the full functionalities and good performance. It well meets the clock requirements of the physical layer of DDR2 controller. The design implemented a four-phase voltage-controlled delay line and make four-phase delay clock, working in the operating frequency, through a full custom designing and the 0.13 ? m CMOS process. The accurate clocks supplied by DLL sample the data from single data rate to double data rate when writing data to SDRAM. Differential voltage-controlled delay line was used to improve the performance of voltage controlled delay line. Simulation results showed that the DLL functioned correctly with good performance. Additionally, fine-tuning and relative testing module were added in the design to facilitate the adjustment and testing. Master and Slaver of Delay-Locked Loop also uses the same structure to reduce design complexity and the circuit area, which makes it easy to be integrated.更多还原