宽带数字监测接收机算法研究及硬件实现

【作者】 王晓；

【导师】 韩春林；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2011， 硕士

【摘要】 无线电频谱监测是无线电频谱管理的重要手段,先进的宽带数字监测接收机为无线电频谱监测提供了有力的保障,因此开发基于软件无线电的宽带数字监测接收机有很大的应用前景。数字化是接收机的发展潮流,数字接收机与模拟接收机相比在可靠性与灵活性上有较大优势。国内的民用数字监测接收机近年来发展较快,但与国外同类产品相比在一些关键性能指标上还存在较大差距,此外在产品可靠性与易用性上也有待进一步提高。本论文以四川省科技计划项目《网络化智能无线频谱监测侦收系统研制》为依托,对宽带数字监测接收机系统的软硬件关键模块进行了深入研究,并初步研制成功了一套宽带数字监测接收机实验系统。本实验系统在设计性能指标上参考了先进的德国R&S公司的全数字式VHF/UHF接收机EM550,数字中频板采用FPGA和DSP作为主要信号处理器件的软件无线电方式,能够灵活的实现多种数字信号处理算法。本论文首先介绍了宽带数字监测接收机的发展动态,然后对适用于宽带数字监测接收机的数字下变频原理以及所涉及的多相滤波、CORDIC、CIC、HB、DA等关键算法进行了论述。接着重点介绍了基于FPGA芯片Stratix II EP2S90F780I4设计的适用于宽带数字监测接收机设计指标的变带宽数字下变频器(Variable-Bandwidth Digital Down-Converter,VB-DDC),并对其中各子模块的FPGA设计实现进行了详细说明。该VB-DDC结合了传统数字下变频结构与多相滤波结构的优点,实现了对输入中频信号的高效高速处理,同时可以根据处理信号带宽要求,通过上位机PC灵活配置寄存器参数并选择下变频器结构为传统下变频结构的窄带DDC或者基于多相滤波结构的宽带DDC,或者联合使用两种结构。当A/D输出中频信号采样率为100MSPS时,本论文中FPGA实现的这种VB-DDC信号处理带宽可在40MHz~150Hz的较大范围内灵活配置,输出基带信号数据率可在50MSPS~763SPS的范围内变化。最后,通过软件仿真和硬件调试结果验证了本论文中VB-DDC的有效性。更多还原

【Abstract】 Radio spectrum monitor is an important way for radio spectrum management. Advanced digital wideband monitoring receivers provide convincing guarantee for radio spectrum monitor, thereby developing digital wideband monitoring receivers based on Software Defined Radio (SDR) technology have large application area in future. Digitization is a trend for receiver evolution. Digital receivers have a big advantage over analog receivers on reliability and flexibility. In recent years, domestic civilian digital monitoring receivers developed rapidly but compared with the foreign productions of the similar type they have big disadvantages in some key performace index. Furthermore, they can be further improved on reliability and convenience.Based on the research project, Intelligent Radio Spectrum Monitoring Receiver Network System, after an in-depth study of the HW/SW key modules used by digital wideband monitoring receivers, this dissertation developed a digital wideband monitoring receiver experimental system. The designed performace index of the experimental system refers to advanced VHF/UHF Digital Wideband Receiver EM550 made by R&S Company in Germany. The Digital IF Board used in the experimental system adopts FPGA and DSP as main signal processing devices and takes advantage of SDR technology. Thereby, multiple digital signal processing algorithms can be realized flexibly.This dissertation first introduces the development of digital wideband monitoring receivers, then presents the theory of Digital Down-Converter,which are suitable for the digital wideband monitoring receiver and related key algorithms such as Poly-phase filter, CORDIC, CIC, HB, DA, etc. This dissertation then focus on the Variable-Bandwidth Digital Down-Converter (VB-DDC) ,which is suitable for Wideband Digital Receiver, is implemented in FPGA chip Stratix II EP2S90F780I4 and depicts each modules that is designed and implemented in FPGA in great detail.The VB-DDC combines the advantages of traditional digital down-conversion architectures and poly-phase filter architectures, realizes efficient high-speed processing for input IF signal, and could configure register parameters flexibly and choose the architecture of the VB-DDC between narrowband DDC based on traditional digital down-conversion architectures or wideband DDC based on poly-phase filter architectures or both of them. When the sampling rate of the output IF signal by A/D is 100MSPS, the processing bandwidth of the VB-DDC could be configured flexibly in the large range of 40MHz~150Hz, and the output data rate of baseband signal could be changed in the range of 50MSPS~763SPS. Finally, software simulation and hardware test results verifies the effectiveness of the VB-DDC in this dissertation.更多还原