【作者】 张昊；

【导师】 韩雁；

【作者基本信息】 浙江大学 ， 微电子学与固体电子学， 2011， 硕士

【摘要】 数字音视频技术在本世纪第一个十年中的蓬勃发展和广泛应用,推动了国内音频数模转换器的研究与开发。在低碳节能的大背景下,功耗问题在要求延长使用时间的便携式电子产品中显得尤为突出；同时,人耳对微弱的噪声十分敏感,为了获得更高的音质,16位到24位的高精度音频数模转换器被广泛使用。因此研发低功耗、高精度音频数模转换器对于满足数字音视频市场需求、提高我国集成电路产业的整体竞争力具有重要意义。在此背景下,本论文设计并实现了一个低功耗、高精度音频数模转换器,完成了从指标定义到流片测试的整套设计流程。本文的主要工作和创新点包括：1.归纳了数模转换器技术,对所采用的∑-△数模转换器进行了系统级分析,确定了整体结构,并深入探讨了模拟电路部分所有模块的工作原理和设计要点,总结了解读工艺和绘制版图的原则和经验,最终设计了一个低功耗、高精度音频数模转换器。其中穿插讨论了混合信号集成电路设计中的若干问题,包括数模电路之间的电平匹配、干扰抑制以及数模整体仿真与验证等。2.在中芯国际0.18μm Mixed-Signal 1P6M CMOS工艺上实现了上述设计,芯片核心面积为1.81 mm2。模拟电路部分的典型信噪失真比为89dB,功耗19.1 mW,其中不含缓冲器的功耗为9.1 mW; DAC整体电路的典型信噪失真比为84 dB,功耗20.3 mW,其中不含缓冲器的功耗为10.3 mW；样片良率为90%。测试结果达到了预期目标。3.对测试后的芯片实施了设计改进,提出了一系列可行方案并进行了仿真验证,这些方案包括高性能带隙基准源、片内参考电压产生和低阈值CMOS开关等。与改进前的仿真结果相比,模拟电路部分的功耗减小了58%,总谐波失真减小了4 dB,为今后的流片提供了有益参考。更多还原

【Abstract】 The prosperous development and wide application of digital audio technology during the first decade of this century has promoted the research and development of audio DAC in China. In the contex of low-carbon energy, the problem of power consumption becomes particularly conspicuous in portable electronic products, which desire the extention of usage time. Meanwhile, human ears are very sensitive to subtle noise, so 16-bit to-24 bit DACs are extensively adopted in order to aquire better sound quality. Therefore, the research and development on low-power, high-resolution audio DAC is extremely important in meeting the needs of market and in the enhancement of IC industry competitiveness of our country.In this context, this dissertation designed and implemented a low-power, high-precision audio DAC and complete the whole design process from the specification definition to tapeout and chip measurement.The main work and innovations include:1. Summarized D/A conversion technology, performed system-level analysis in the adopted∑-Δstrucuture and determined the overall structure, then deeply discussed the operation principles and design key points of all the modules in the analog part, summarized the principles and experience on how to understand the fabrication process and how to draw the layout, and finally designed a low-power, high-precision audio DAC. There are discussions about several problems in mixed-signal IC design among these chapters, such as the level matching, the inference supression between digital part and analog part, the mixed-signal simulation and layout verification, and so on.2. This design is implemented in SMIC 0.18μm Mixed-Signal 1P6M CMOS process, the core area is 1.81 mm2. The typical SNDR of analog part is 89 dB, which consumes 19.1 mW, and this number decreases to 9.1 mW without buffers. The typical SNDR of the whole DAC is 84 dB, which consumes 20.3 mW, and this number decreases to 10.3 mW without buffers. Besides, the prototype yield is 90%. The measured resultes achieved our expected goals.3. Performed the design improvement after chip tests and proposed a series of feasible schemes, including high-performance bandgap reference, the generation of on-chip reference voltage and its buffering, low threshold voltage CMOS switch, and so forth. Compared to the simulation result of former version, these schemes reduce the power consumption of analog part by 58% and decrease THD by 4 dB, which provided useful reference to future work.更多还原