【作者】 杨光；

【导师】 靖固；

【作者基本信息】 哈尔滨理工大学 ， 计算机应用技术， 2010， 硕士

【摘要】 随着集成电路工艺的发展,以IP(Intellectual Property)核复用技术为支撑的片上系统SOC(System-On-Chip)技术正得到飞速发展。SOC测试就成为了其应用的主要的瓶颈。本文从SOC可测试性设计出发,针对多核SOC的基本测试结构,即从测试外壳,测试访问机制设计以及测试调度问题三个方面进行分析和研究。当IP核被集成到SOC芯片后,原有可测的端口失去了原本的可控性和可观测性而无法进行测试,必须为嵌入到SOC中的IP核提供相应的测试访问路径。测试访问机制就是在测试源与测试沉之间提供这样的路径;IEEEstd1500配置的测试外壳为嵌入式IP核与测试访问机制之间建立了交互界面,它可提供多种操作模式;测试调度则决定了SOC中每个IP核的测试顺序及需要使用的测试资源SOC芯片的测试时间最小化。本文介绍了IEEEstd1500的测试外壳结构的实现过程。由于系统芯片的不同测试访问机制也有所不同,文中对各种测试访问机制和测试调度的优缺点进行了比较,详细介绍了当前应用较为广泛的基于测试总线的测试访问机制和基于遗传算法的测试调度。在此基础上提出了基于IEEEstd1500测试外壳与测试总线两级协同控制实现测试访问机制的功能。通过优化神经网络以解决SOC的测试调度问题。实现最小化SOC的测试时间。通过仿真和实际测试的结果来看,文中研究与设计的测试访问机制和测试调度算法为多核SOC测试提供了适宜的测试结构与设计方法,降低了SOC测试的难度和成本。更多还原

【Abstract】 With the progress of semiconductor process and design level, IP design industry has been entered the system-on-chip SOC era. Single chip integration of a greater number of transistors, can complete the more complex functions. This dissertation mainly discusses the general test architectures of SOC and expands on three sub problem, test wrapper design, test access mechanism design and test scheduling.System-on-ship SOC integrated circuits composed of processors, memories, and periripheral interface devices in the form of embedded cores, are now commonplace. First, the number of input/output pins in a chip cannot keep pace with the growth of the number of cores inside a chip. To reduce the hardware production and test cost, it is preferred to reduce the number of pins of a chip. This, unforthunately, implies that the test access time will be longer due to the delay time and limited test paths from the primary input/output to the core under test. This is called the TAM (Test Access Mechanism) limitation. The current SOC chips are two salient features of large-scale and large number of embedded IP core. The I/O ports of IP core can not be accessed directly by the SOC’pins for the IP core embedded in the SOC. Therefore, test access mechanism which provides a channel from test resource to test sink is needed;test wrapper is an interface between TAM and IP core, which can control the IP core operating mode; test scheduling is a process to determine the beginning and the end time of testing each IP core to minimize the total test time. As for SOC test, when the designer or integrator of SOC system have received the chip core, the most important problems need to be solved is to put the chip into market by test scheduling, which decides the test turns and resources of each chip core. Generally, we focus on the research on finding the optimal solution for solving the SOC test scheduling problems. The paper use the constructed neural network combined with genetic algorithm to find the optimal solutions within reasonable computing time. Through the researches mentioned above, the test architecture, optimization method and test scheme are provided for SOC to reduce both difficulties and costs of SOC test.更多还原