高速时钟数据恢复系统的研究

【作者】 王勇；

【导师】 许俊；

【作者基本信息】 复旦大学 ， 电子与通信工程， 2009， 硕士

【摘要】 随着传输数据速率不断提高,高速串行收发器得到了越来越多的应用。在串行收发器中,时钟数据恢复系统是它的核心电路。本文采用了基于半数字双环路的时钟数据恢复系统,并对它进行了理论分析和芯片验证。在本文中,我们详细讨论一阶和二阶时钟数据恢复系统的特性,并用二个芯片来验证时钟数据恢复系统的理论分析。其中一个芯片使用了一阶时钟数据恢复系统,满足4.8Gb/s的串行传输速率要求。另外一个芯片使用了二阶时钟数据恢复系统,满足6Gb/s的传输速率要求。这二个芯片测试结果与理论分析基本一致。本文在芯片实现上提出了一些创新性的电路。首先,一个新颖的快速锁定电路得到了应用,它使时钟数据恢复系统正确并快速地到达锁定状态。其次,在二阶时钟数据恢复系统中,我们创新性提出了一种减少环路延迟的电路结构,提高了环路的性能。这二个芯片都实现了高性能和低功耗的设计目标,并已经开始大批量供货。更多还原

【Abstract】 Recently, serial transceiver develops rapidly with the increasing data speed requirement. The CDR(clock data recovery) is most critical circuits in transceiver, and we will discuss the CDR in this thesis. The CDR using in this thesis is base on semi-digital dual loop CDR architecture. The theory analyze is done firstly, then the chip is designed to verify with the theory analyze. The features of first order and second order CDR will be discussed in detail. Two chips are designed. One uses the first order CDR for 4. 8Gb/s serial transceiver. Another chip uses the second order CDR for 6Gb/s serial transceiver. The measurement result of chips is consistent with the theory analyze. A new circuit is used for fast-lock, CDR will be acquired fast lock correctly with this circuit. A novel architecture is used in the second order CDR for decreasing the loop delay to improve the performance of CDR. Those chips meet the requirement of high performance and low power. Chips have been in mass production status.更多还原