【作者】 谈飞洋；

【导师】 杨银堂；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 本课题设计的高速ECC算法协处理器用于满足大型认证服务器的高数据吞吐量的需求。其中,ECC算法芯片的吞吐率是解决服务器高数据吞吐量的关键。本课题的主要研究任务是高速ECC算法协处理器的算法改进以及硬件实现。本课题研究的ECC算法实现了位长192-bit到256-bit模p素域上的通用椭圆曲线的运算。在硬件设计上,优化了流水脉动双模乘器结构;在算法级上,采用了改进的Mongtomery模乘算法,该算法突破了原Montgomery算法中的“最后减法”和“商计算”的瓶颈,解决了“商计算”的流水延迟和点运算的有限域算术运算输入输出数据溢出问题;同时,ECC点运算采用“从左到右”点乘算法,点乘运算中需要的随机数采用NAF2编码,上点的坐标表示采用Modified Jacobian混合坐标,有效地减少了点加运算次数。为了提高流水脉动双模乘器硬件效率和点乘运算速度,本课题重新排列点加和点倍运算序列,通过状态机调用序列指令的方式实现ECC中的点运算,使得点加运算只占用7个模乘计算周期,点倍运算只占用4个模乘计算周期,从而实现了高速ECC点乘算法平均模乘计算周期数为6.3L(L近似为模长)。本设计实现的芯片能够实现在工作频率为100MHz,模长为192-bit时,平均每秒点乘运算约为6000次;模长为256-bit时,平均每秒点乘运算约为3000次。更多还原

【Abstract】 According to the requirement of the high data throughput of authorization service, ECC public-key cryptosystems based high-speed ECC chip is an effective solution. In which, the throughout of ECC chip plays an important role in ECC public-key cryptosystems. To improve the throughout of ECC chip, the main research task of the thesis is a high-speed hardware implementation of ECC algorithm.This thesis presents ECC algorithm which implements the operation of general Elliptic curve defined over the prime field . In algorithm level, hardware implementation of ECC algorithm is based on the dual modular multiplier architecture with pipeline and systolic. Modular multiplication algorithm is the improved Montgomery algorithm. The algorithm breaks up the bottleneck of Montgomery algorithm formed by“no final subtractions”and“quotient determination”. Point multiplication algorithm is“from left to right”algorithm, in which, recoding is Non Adjacent Form(NAF). The point coordinate representation of point over is Modified Jacobian Maxed coordinates. For improving the hardware efficiency of the pipeline and systolic dual modular multiplier, this thesis rearranges the operation sequence, then makes point addition need 7 modular multiplication cycles and point doubling need 4 modular multiplication cycles. In high-speed ECC, the modular multiplication cycle of point multiplication algorithm are 6.3L(L approximately equals the modular bit-length).The high-speed hardware implementation of ECC algorithm applies to the ECC ASIC high chip.With the frequency of chip 100 MHz. and 192-bit prime modulus, it performs 6000 times point multiplication operation per second. For 256-bit prime modulus, it performs 3000 times point multiplication operation per second.更多还原