【作者】 马亮；

【导师】 高明伦； 张多利；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2009， 硕士

【摘要】 MPEG-4是基于第二代视频压缩编码技术制定的标准,它采用了一系列创新性的技术,在压缩效率和灵活性方面比先前的标准有了明显的改善。MPEG-4凭借其低码率高质量的优点,广泛应用在多媒体传输、存储和检索等领域。运动补偿是利用先前已编码帧的图像作为参考图像对当前图像进行预测的一种方式。在MPEG-4中引入了先进的运动补偿算法,其中包括4-MV(FourMotion Vectors,四运动矢量)模式,直接模式,无限制运动补偿,1/4像素精度运动补偿等以前没有的工具集。这些算法可以获得更高的编码效率和更优的图像质量,但也为VLSI设计和实现增加了难度。本文研究了MPEG-4运动补偿电路的VLSI设计与实现方法,完成的主要工作包括以下几个方面:(1)体系结构的设计:采用了自顶向下的方法,将运动补偿电路具体划分为运动矢量解码模块、地址产生模块、像素预测模块和重建模块四个子模块,然后对四个子模块进行了详细的设计和说明,包括介绍子模块的功能、内部硬件结构以及操作时序等。(2)关键功能模块的优化实现研究:针对运动补偿模块数据运算量大和访问帧存储器频繁的特点,采用四个插值单元同时处理,增加像素缓冲器,充分利用并行性结构等方法来加快运动补偿速度。(3)关键算法的改进和优化研究:对4-MV模式和直接模式的运动矢量预测,无限制运动补偿,1/4像素插值等关键算法的实现进行了详细的讨论。特别的,在4-MV模式运动矢量预测部分采用行存储策略和对无限制运动补偿提出了坐标转换法,节省了存储器资源。(4)FPGA原型实现及基于硬件原型的功能验证实践:针对运动补偿模块的功能验证情况多和整体性强的特点,提出了软件仿真验证和FPGA原型验证相结合的联合验证的方法。整个设计采用Verilog HDL语言描述,通过了现场可编程门阵列(FPGA)的原型验证,并采用SIMC0.18μm工艺单元库完成了该电路的逻辑综合。经过实际视频码流测试,本设计可以达到MPEG-4简单类和高级简单类的实时解码的技术要求。更多还原

【Abstract】 MPEG-4 is a multimedia compression standard based on the secondary generation visual coded technology.It has adopted a lot of creative technologies,so the code efficiency and flexibility have been greatly improved than the previously standards.MPEG-4 standard has been applied broadly in the domains of multimedia transmission,storage and searches,with its advantages such as low bit-rate and high compression.Motion compensation is a method which uses the coded picture for reference picture to interpolate the current picture.Lots of new algorithms,such as 4-MV method,directed method,quarter-pixel motion compensation,unrestricted motion compensation and so on,are adopted by the motion compensation tool of MPEG-4. These can enhance the video quality and code efficiency,but increase the difficulty for VLSI design and implementation.The main object of this thesis discusses the VLSI design and implementation of motion compensation for MPEG-4 decoder.The contributions of the essay are summered as followed:(1) The research on the architecture design:With Top-Down method,the motion compensation circuit was divided into four sub-modules:motion vector decoder,address generation module,pixel interpolation module and reconstruction module.Then the four sub-modules were detailed, include the function,the hardware architecture and operation timing.(2) Researches on the optimization design of the key modules:For the motion compensation is the most intensive part of accessing memory and has high throughput,several methods were adopted to improve memory access efficiency,including four pixel interpolator,pixel buffer augmentation,and parallel architecture,which lead to good speedup of motion compensation.(3) Study and optimization of some major algorithms of motion compensation.The implementations of 4-MV method,directed method, quarter-pel motion compensation,and unrestricted motion compensation were discussed in detail.The methods were proposed which can reduce memory consumption for motion vector decoding in 4-MV and unrestricted motion compensation respectively.As for the former,a line buffer is adopted instead of frame buffer,and for the later,a method of coordinate transformation is used.(4) Practices on FPGA prototype implementation and function verification: The function verification of motion compensation module has such characteristics as excessive test suits,sea of test data,and high correlation between sub-modules,so the combination of software based simulation and FPGA prototype based emulation was adopted as the principal verification methodology in our design.The design was described with Verilog HDL.It has been implemented by Field Programmable Gate Array(FPGA).Synthesis was also fulfilled with Synopsys Design compiler,based on SMIC 0.18μm standard cell CMOS technology.Demo experiment with real video stream,shows that the design can meet the real-time decoding requirements of the MPEG-4 simple profile and advanced simple profile.更多还原