【作者】 王波；

【导师】 阔永红；

【作者基本信息】 西安电子科技大学 ， 通信与信息系统， 2009， 硕士

【摘要】 现代通信朝着全网IP化的进程逐步发展,越来越多的通信需要IP路由查找;同时光纤技术的发展,使得比特速率达到了20Gbps,路由技术成了整个通信系统的瓶颈,迫切需要一种具有高查找性能,低成本的路由算法,能够适应大规模应用。本文研究了一种高性能、低成本的路由算法。在四分支并行路由查找算法的基础上,实现了双分支并行,每个分支流水查找的16-8-8路由算法。该算法由三级表构成,长度小于16的前缀通过扩展成为长度16的前缀存储在第一级表中;长度小于24位的前缀通过扩展成为长度24的前缀存储在前两级表中;长度大于24的前缀则通过专门的存储空间进行存储。将IP路由的二维查找转化为一维精确查找,每次查找最多访问存储器3次,就可以查得下一跳的路由信息。使用Verilog语言实现了本文提出的算法,并对算法进行了功能仿真。为了实现低成本,该算法采用了FPGA和SSRAM的硬件结构实现。功能仿真表明本文设计的算法查找速度能适应20Gbps的接口转发速率。更多还原

【Abstract】 With the proceeding of the realization by IP networks in modern communication system, the IP lookup algorithm is used widely. With the development of fiber technology, the bit rate can get to 20Gbps. Based on those, route technology turns into the bottleneck in communication system. It is important to find a routing algorithm with high performance and low cost, which can be used widely.The thesis researches on a routing algorithm with high performance and low cost. Based on the four branches parallel route algorithm, a two-branch parallel 16-8-8 route algorithm is realized in the thesis, each branch being processed in pipeline. There are 3 tables, the prefixes less than 16 being expanded to 16, are stored in table 1. Those less than 24 being expanded to 24, are stored in table 1 and table 2. The prefixes more than 24 are stored in special units. The algorithm transforms the two-dimension lookup table into one-dimension table. It needs no more than 3 times to access the register to get the next routing information. The algorithm is simulated by Verilog language. In order to reduce cost, the algorithm is realized on FPGA and SSRAM.Based on the results of functional simulation, the algorithm can support up to 20Gbps bit rate.更多还原