【作者】 陈博明；

【导师】 周敬利；

【作者基本信息】 华中科技大学 ， 计算机系统结构， 2007， 硕士

【摘要】 数字信号处理器(DSP,Digital Signal Processor)正在视频处理领域得到越来越广泛的应用。以DSP为基础的嵌入式视频编解码器也正成为研究与应用的热点。多个功能单元、取指取数分离的哈佛总线结构、非常有限的存储资源、片上内存与片外内存访问速度差别巨大的分级存储系统等DSP特有的体系结构特点为视频编解码技术的发展提供了机遇与挑战。结合DSP的体系结构及实时操作系统(RTOS,Real-Time Operation System)的特点,在保证实时、最小化存储器需求、最小化功耗需求、增强解码器负载自适应性等方面,从数据布局优化、多任务调度策略角度出发,对嵌入式MEPG-4视频编解码器的设计与优化进行了研究。变长码表占据了编码器很大一部分的存储空间,且串行特点正逐步使变长编码成为DSP视频编码的瓶颈。针对DSP体系结构特点,从数据布局优化的角度出发,采用重新排列码表的方法,对变长编码算法进行改进。对帧内宏块的交流系数及帧间宏块的直流、交流系数的变长码表采用间接索引。同时针对DSP体系结构、RTOS及TCP/IP协议栈的特点,在多任务调度策略的基础上,在解码器端设计了低复杂度的拼帧策略、缓冲区控制策略及多路接收策略,以解决视频数据出错、到达速率抖动的问题,同时使多路视频解码器能够同时从多个不同的源(IP地址不同)取得数据。改进后的码表所需的存储空间降为原来的1.25%,便于将码表的存储位置由片上移至片内。在进行4路500bps的CIF(Catch in Focus)视频解码时,通过调节参数,可动态调整CPU负载从12%至75%,使编解码器与不同负载相适应,同时可找到使CPU负载标准差尽可能最小的点,即编解码器稳定运行的最佳点。更多还原

【Abstract】 DSP (Digital Signal Processor) is well on the way to be more and more widely used in video processing and the embedded video CODEC (enCOder/DECoder) based on DSP is one hot spot in research and applications. The characteristics of DSP architecture, such as eight functional units, enhanced Harvard architecture, limited storage, and speed gab between on-chip access and off-chip access, are the challenges of video coding and decoding. According to the characteristics of DSP architecture and RTOS (Real-Time Operation System), a MPEG-4 CODEC is designed and optimized to meet the real-time demand, minimize the storage and power, and enhance adaptive capability.The VLC (Variable Length Coding) code table consumes much storage resource, and VLC is becoming the choke point of video coding on DSP because of its serial characteristic. So the VLC is improved by reorganizing the VLC code table from the point of view of memory arrangement. Intra VLC table and inter VLC table are both indirect-indexed. Also the strategy of frame form, buffer control and multichannel receive based on multitask scheduling is studied and implemented in order to solve the problem of data error and data-arrive jittering and to make sure the CODEC can fetch data simultaneously from different sources, which have different IP addresses.The size of the reorganized VLC tables is 1.25% of the old table and it can be put into the on-chip memory. The DSP CPU load can be 12% ~ 75% to adapt for different decoder’s load through adjusting the parameter when decoding 4-channel compressed CIF video stream at 500bps. Also the right point that make the std of CPU load approximately smallest can be found, and that is the approximately optimal point of decoder stabilization.更多还原