【作者】 王娜；

【导师】 王进祥；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 未来航天任务需要在科学仪器、大容量内存、计算机以及上下行链路间进行大量的数据交换,必然要求卫星内部通信具有更高的处理速度、可靠性、抗辐照能力及高速的错误检测及错误恢复能力。将各个独立的电子仪器设备连接到一起的星载数据总线在整个系统中有着举足轻重的地位。它的速度、使用的灵活性以及可靠性将直接影响航天器的整体性能。SpaceWire总线是一种高速的、点对点、全双工的串行总线网络,它汲取了1394技术、ATM技术和以太网技术的优点,同时考虑了空间应用的特点,除具有很好的EMC(电磁兼容)特性之外,在错误检测、异常处理、故障保护和故障恢复及时间确定性方面做了相应加强,可以满足未来高性能高速数据传输的需求。论文对课题的目的和意义进行了简单介绍,以及SpaceWire总线的发展现状及前景,介绍了SpaceWire总线的特点并与其他高速串行总线进行了简要对比。因为在本设计中SpaceWire接口连接于APB(AMBA外设总线)总线上,作为主机系统与SpaceWire总线网络之间的桥梁,在主机一方遵循以APB为主体的接口协议,同时在SpaceWire总线网络一方遵循ECSS-E-50-12A的点对点接口协议,所以对AMBA总线协议和SpaceWire总线标准分别进行了较为详细的描述。然后,介绍了SpaceWire总线接口的设计:给出了设计的SpaceWire接口的总体框架图;并按照自顶向下的设计流程,分模块对该设计的各个子模块的功能和设计方法进行了进一步的介绍;对设计中涉及到的比较独特的机制做了详细说明。由于系统验证平台在整个设计中具有非常重要的作用,所以,接下来介绍了怎样利用AMBA APB总线功能模型(BFM)搭建验证平台,并编写测试激励对设计进行功能验证,给出了验证结果。利用Synopsys公司的Design Compiler完成了设计的逻辑综合,给出了时序报告和面积报告。最后进行了时序分析与综合后仿真。更多还原

【Abstract】 Future space tasks need to transmit a huge number of data between science instruments, mass-memory units, computer and downlinks, so the communication in the spacecraft must be very exactitude in speed, agility, abnormity managing, fault protection and fault renewing. The spacecraft bus that connects absolute electronic equipments together will be very important. Its speed, agility and reliability will infect the whole performance of the spacecraft directly.SpaceWire is a high-speed, point to point, full-duplex, serial bus network that taking the advantages of FireWire, ATM and Ethernet. Considering the specialty of the space application, SpaceWire is enhanced in EMC(electronic and ground compatible), mistakes searching, abnormity managing, fault protection and fault renewing to meet the needs of future, high capability, high speed data transmission.Firstly, the purpose of the thesis was briefly introduced. The development of SpaceWire was summarized. The characters of SpaceWire and other high-speed bus were also introduced and briefly compared. Secondly, in this design, as the bridge between SpaceWire network and the host, the SpaceWire interface is connected to the APB bus. So, it keeps to the ECSS-E-50-12A standard in the side of the SpaceWire network, but AMBA on-chip bus standard in the side of the host. Because of this, the ECSS-E-50-12A standard and the AMBA on-chip bus standard were described detailed in this thesis. In the following design implementation, the design is modeled at RTL level with Verilog HDL in Top-Down design methodology, and give out a detailed description of the special methods. In the end, utilizing the APB bus function model (BFM) thought, the thesis builds a simulation environment to finish the function verification. In addition, the thesis has achieved the gate level functional and timing verification using gate level netlist and SDF timing information after the logic synthesis of the router design.更多还原