【作者】 雷晓荃；

【导师】 毛陆虹；

【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 甚短距离传输(VSR)是一种用于短距离(约300m～600 m)内进行帧数据光传输的系统,主要应用于交换机、核心路由器(CR)、分插复用器(ADM)和波分复用(WDM)终端等网络中不同层次设备之间的互连,具有构建方便、性能稳定和成本低等优点,是解决局内光互连性价比最好的方案。VSR4-3.0是面向短距离内STM-64/OC-192帧的互联要求提出的并行光接口标准之一,它只需要用1条光缆就能进行双向互连,使用起来更方便,所用器件的体积也更小,具有很好的发展前途。本论文深入分析了VSR4-3.0并行光传输标准,重点研究了该系统的核心部分——转换器集成电路在现场可编程阵列FPGA(Field Programmable Gate Array)上的设计和实现。采用模块化设计方法,用Verilog硬件描述语言编写了帧定位、帧同步、通道去斜移等模块代码。结合四路通道并行传输STM-64/OC-192帧数据的特点,参考ITU-T的G.783建议中对SDH帧同步性能的要求,对帧同步模块的关键参数做了详细的计算,分析和选择。使用Altera公司的Quartus II5.0 EDA开发工具对所有电路实现了面向FPGA的逻辑综合和优化、布局布线,时序仿真和静态时序分析。针对系统部分模块提出了改进和优化方案:采用单比特容错技术提高帧同步系统的抗误码干扰能力;采用格雷码技术减少帧定位计数器的毛刺;采用流水线方法设计数据选择阵列,提高系统运行速度。本文所有的设计均在Altera Stratix GX系列FPGA的EP1SGX25F1020C7上实现,给出了各模块的结构框图和仿真结果。仿真的结果表明,所有的设计均能正确的实现各自的功能,完全能够满足10Gb/s高速并行传输系统的要求。更多还原

【Abstract】 Very short reach (VSR) is an optical transmission technology to transmit data over a short distance (about 300m~600m). It is mainly used to link two equipments of different network layers,such as Switch,CR,OXC,ADM and WDM terminals. It has the advantage of easy constructing,stable performance and low cost. OIF-VSR4-3.0 is a parallel optical transmission interface with 4 channels to transmit and another 4 channels to receive the STM-64/OC-192 frame over‘very short’distances. It only needs one 12-fiber cable to implement bidirectional transmission. The size of its device is smaller. So it has a good development prospect.In this paper, OIF-VSR4-3.0 parallel optical transmission protocol is deeply studied. The converter IC of VSR system according to this standard is designed, and implemented by using FPGA. With the blocking design method, codes of some function modules are compiled with Verilog hardware description language, such as frame aligner module, frame synchronization module and channel skew remove module. On the base of the characters of STM-64/OC-192 data through the 4 data channels,and the requirement of G.783 recommendation to the SDH frame synchronizing performance, key parameters are chose by calculating and analyzing. Altera’s development kit Quartus II5.0 is used to complete logic synthesis & optimization, placement & routing, timing simulation, and timing analyzer of all the circuits.Some advices are given to optimize the operation of the converter IC. One bit error-tolerance technique is analyzed to enhance the detection velocity and the reliability of the frame synchronization system. Gray code technique is used in frame orientation counter to solve the burr problem. Pipelining design method is introduced in large-scale Multiplexer to raise the circuit frequency.All designs in this paper are realized using EP1SGX25F1020C7 FPGA of Altera Stratix GX series. The structures and simulation results of modules are presented. Through the results, we can draw the conclusion that all of the designs can correctly implement their functions and meet the requests of 10Gbit/s high-speed parallel optical transmission system.更多还原