【作者】 张奇惠；

【导师】 张伟风；

【作者基本信息】 河南大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 随着多媒体技术的快速发展,静止图像的应用越来越广泛。它的应用主要集中在图像的存储和图像的传输两方面,但是从具体应用中我们可以发现当模拟量数字化后其频带大大加宽,数码率非常高,静止图像占用了越来越多的存储空间。在这样的条件下,静止图像的压缩成为了一个研究的热点。目前静止图像的压缩算法以JPEG和JPEG2000为主。本论文采用JPEG标准,完成了JPEG编码算法的芯片设计。论文首先阐述了JPEG压缩算法的基本理论;其次用软件的方法验证了这套理论的可行性;然后完成了JPEG算法的ASIC(Application Specific Integrated Circuit)芯片设计,包括整体结构设计、各模块的结构设计、仿真验证、综合、版图设计以及形式验证等。本论文课题的芯片设计利用Verilog硬件描述语言和多种EDA(Electronic Design Automatic)工具完成的。按照正向设计的流程,最终得出了芯片整体电路的网表和版图。本芯片总门数相当于三十万门左右的标准单元,仿真时钟频率为100MHz,软件验证压缩率约为9:1。更多还原

【Abstract】 The still image compression has a sound development with the rapid application of multi media technique. Its application mainly focuses on the store and transmission of images, but we find that its frequency band will be widely increased, the bit rate is very high, and the still images occupy more and more space when the analog value is digitized.The most popular algorthem by now is JPEG, which is mainly referred to baseline mode JPEG and JPEG2000 in this thesis.Here we implemente an ASIC chip of JPEG standard. In this paper, we firstly introduce the theory of JPEG compression algorithm. Afterwards, we verify the feasibility of this theory in software. In the last part, we give the detailed implementation of our ASIC chip, including global architecture design, module design, simulation, synthesis, physical layout and formal verification. In the every step, an elaborate analysis is presented.This design of this paper is implemented by Verilog hardware description language and various eda tools.At last,we obtain the netlist and GDSII file of the design.According to the reports, our layout amounts to about 300 thousand standard cells and the chip can run at 100 MHz,the compression ratio is about 9:1 by software verification.更多还原