【作者】 贺珊；

【导师】 高明伦； 张多利；

【作者基本信息】 合肥工业大学 ， 电路与系统， 2007， 硕士

【摘要】 随着科技的发展，半导体工艺制程进入超深亚微米时代，在一个芯片上集成上百万甚至上亿个晶体管成为现实。当集成规模发展到可以将整个数字计算机系统集成到一块芯片上时，系统芯片(SoC，System-on-a-Chip)应运而生，并且迅速成为大规模数字集成电路的主导。SoC在带来诸多优点的同时，也对现有的设计与验证技术提出了新的挑战。目前，普遍认为IP核重用技术是解决SoC产品设计规模与面市时间之间矛盾的有效途径，可以充分地发挥SoC的优势。散逻辑和状态机是IP核设计中两种常用的描述方法。在验证技术方面，更高抽象层次的方法如基于事务级的验证越来越受到业界的重视。本文根据IIC总线协议规范，使用基于散逻辑的描述方法设计了一个完整的IIC总线接口IP软核；并围绕IP核的验证问题，在研究了当前主要功能验证方法和技术的基础上，对本文所设计的IP核进行了全面的功能验证。论文主要研究工作和取得的成果如下：1、对基于散逻辑与基于状态机的设计方法进行了对比研究，分析了IIC总线协议规范，使用基于散逻辑的设计方法成功设计出一款功能实现比较完全的IIC总线接口IP；2、在基于重用的功能验证方法学的指导下，使用Verilog语言，为本文所设计的IP核搭建了基于BFM(Bus Functional Model)的功能验证平台；3、研究了功能验证的基本方法和相关研究的进展情况，在基于事务的验证方法学的指导下，使用Synopsys新推出的硬件验证语言——OpenVera，以IIC总线接口IP核为实例，搭建了功能验证平台，并与使用传统方法所搭建的验证平台进行了性能对比。对比结果表明，新的验证语言及验证方法可以获得更高的验证性能。更多还原

【Abstract】 With the development of semiconductor technics, the design of integrated circuit has entered into sub-micron era and chips with millions of transistors have become common. When the whole digital computer system can be integrated into one chip, SoC (System on Chip) has bcome an inevitable result of the current technology trend. As SoC presents a lot of advantages, it also puts forward new challenges to the design and verification of circuits.Reusable IP is considered a good solution to the complexity of SoC and the time pressure from market. Random-logic and finite-state-machine are two main description methods in IP design. On the other hand, the verification method based on transaction have been paid more and more attention. In this thesis, an integrated IIC Bus interface IP is designed based on random-logic according to IIC Bus’s specification. Some functional verification methodologies are studied, and a complete testbench for the IIC Bus interface IP is constructed. Main works and achievements are as follows:Firstly, two design methods are compared, one is based on random-logic and the other is based on finite-state-machine, then an IIC bus interface IP with relatively full functions is designed based on random-logic.Secondly, under the guidance of the functional verification methodology which is based on IP reuse, a testbench of the IIC interface IP based on BFM is constructed with Verilog HDL.Finally, basic methods of functional verification and relevant development are studied. A testbench is established using a new Hardware Verification Language named "OpenVera" which is presented by Synopsys. The performance of the new testbench is compared with that of traditional methods. The results of the comparison indicate the new verification language and method improve the performance of functional verification.更多还原