基于CFCS的MDAC研究与设计

【作者】 范龙；

【导师】 李竞春；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 随着无线通信、视频处理与数字技术的蓬勃发展,人们对低功耗、高精度和高速度的ADC集成电路需求与日剧增。本文针对12位100MSPS流水线ADC中的关键模块MDAC进行了深入的研究,并采用了一种CFCS(交换反馈电容开关)技术,全面提高了系统性能。首先,详细分析了MDAC对系统引入的主要误差机理,并综合考虑了各方面性能的折衷,合理分配各级级精度。为了进一步减小功耗优化性能,引入按比例逐级缩减技术,优化了系统结构。其次,对CFCS技术作了完整的理论分析,并基于该技术提出了合理的MDAC系统结构。与传统技术相比,CFCS技术能降低系统对电容匹配精度的要求,实现更高的线性度。为了从电路上实现该技术,本文所设计的MDAC修改了传统的电容阵列,并设计了新的编码电路。然后,在实际的电路设计中,采用两级运放作为MDAC中的主运放,能够得到高增益和高输出摆幅,并通过使用调零电阻抵消零极点的密勒补偿技术,得到大单位增益带宽和合适的相位裕度;设计了连续型和开关电容型共模反馈电路,并分别应用于运放两级的输出端。最后,基于SMIC 0.18μm/3.3V硅CMOS工艺模型,通过Cadence模拟软件对各级MDAC进行了模拟仿真。结果表明,各级MDAC都能在100MHz的采样频率下满足ADC系统对这些MDAC单元模块的指标要求。以第一级MDAC为例,它的运算放大器低频增益达到89.2dB,单位增益带宽达到2.12GHz,相位裕度为26°,符合最小建立的要求。在瞬态仿真中,第一级MDAC的建立时间仅4.47ns,建立精度为499.4mV,转换速率达到586V/μs。研究结果表明,本MDAC能通过CFCS技术抑制电容失配误差,并达到了12位100MSPS流水线ADC的指标要求。更多还原

【Abstract】 The increasing demand for low-power high-speed and high-resolution ADC ICs becomes obvious, resulting from rising applications in wireless communication, video process and countless of digital devices. In this dissertation, a in-depth and detail research for the key module MDAC built-in 12-bit 100MSPS pipelinede ADC has been done. A new CFCS (Commutated Feedback-Capacitor Switching) technique is introduced into this module to improve systemic performance.Firstly, a detailed analysis of dominant error mechanisms introduced into the system by MDAC is provided. Given a full consideration of the performance, stage resolution is distributed to every stage. In order to reduce power dissipation further, as a useful method scaling down technique is adopted to optimize systemic structure.Secondly, a complete theory analysis of CFCS technique is finished, and a reasonable MDAC systemic structure is presented. Compared with traditional technique, CFCS relaxes the capacitor matching resquirement and gets higher linearity. To realize this technique in circuit, traditional capacitor array has been modifies and a new encoder has been conceived in the MDAC.Thirdly, during the process of circuit designing, a two-stage amplifier is proposed as the main amplifier in MDAC, which has high gain and high output swing. Pole-zero canceling with a resistor is adopted to get wide GBW and appropriate PM. continuous-time and switch-capacitor common-mode feedback are designed, and used to the output of two stages respectively.Lastly, the MDAC has been simulated by Cadence EDA software with standard SMIC 0.35um/3.3V Si-CMOS process model. The results show that every MDAC satisfies the requirement of ADC system at 100MHz sampling frequency. Taking the first stage MDAC as example, its main amplifier DC gain is 89.2dB, GBW is 2.21GHz, PM is 26°. During time domain simulation, its settling time is 4.47ns, settling resolution is 499.4mV, slew rate is 586V/μs.Therefore, this MDAC can reduce capacitor mismatching error by CFCS and fullfill the requirement of 12-bit 100MSPS pipelined ADC.更多还原