节点文献
多模式高效单片同步BUCK型DC/DC稳压器的设计与实现
Design and Implementation of Multi-Mode High-Efficiency Synchronous BUCK DC/DC Convertern
【作者】 郭文雄;
【导师】 李勇;
【作者基本信息】 西北工业大学 , 软件工程, 2007, 硕士
【摘要】 本论文主要研究了BiCMOS工艺下DC/DC稳压器的设计与实现。 论文主要讨论了BUCK型DC/DC稳压器的系统设计、电路设计、版图设计和性能仿真,设计了多模式高效同步BUCK型DC/DC稳压器XD8183。设计中采用电流模脉宽调制方案,提高了芯片在电源电压和负载变化时的瞬态响应性能;采用分段线性斜坡补偿电路,消除了电流模DC/DC稳压器中占空比大于50%时出现的开环不稳定、亚谐波振荡、响应不够理想及对噪声敏感等缺点;采用锁相环技术,实现了开关频率外同步的功能,减小了分布式电源系统中其它电源对该芯片造成的影响,频率捕获范围为1.1~1.9MHz;采用脉冲跳跃、突发和频率外同步三种工作模式,适应了不同的应用要求,将芯片的特点发挥到最佳。XD8183还集成了过流保护和过温保护等功能。 论文还分析了模拟IC版图设计中的关键因素,采用0.6μm BiCMOS工艺设计了XD8183的版图,并对该版图进行了后级仿真。仿真结果表明:电源转换效率达到96%;芯片在工作期间静态电流仅为10μA,而在关断模式下则降到1μA;工作频率恒定为1.5MHz。主要性能指标满足设计要求,可在工艺线上进行投片。
【Abstract】 This thesis mainly studies the design and implementation of BiCMOS DC/DC converters.Systematic design, circuit design, layout design and performance simulation of Buck DC/DC converter are comprehensively presented at first. Then, on basis of these analyses, the XD8183 that is a multi-mode high-efficiency buck DC/DC converter is fabricated. Because of adopting current-mode control in the design process, the transient response speed of the supply voltage and the load variety become faster; owing to adopting the piecewise linear slope compensation circuit, the disadvantages of current-mode control when the duty cycle is greater than 0.5, such as instability of open-loop, sub-harmonic oscillation, non-ideal loop response and an increased sensitivity to noise are eliminated; for adopting the phase-lock loop to the chip, the function of outer synchronization is realized, which is helpful to reduce the interference from other power supplies in the distributed power system, and the frequency capture ranges from 1.1MHz to 1.9MHz; since adopting pulse skipping mode, burst mode and outer synchronization, the operation mode can be chosen according to different applications, which makes full use of the chip’s advantages. In addition, lots of protection circuits are integrated in the chip, such as over current protection, thermal shutdown, and so on.Furthermore, the thesis analyses the core factors that should be considered in layout design for analog IC. The layout of XD8183 is schemed out based on 0.6μm BiCMOS process, and it passes the post simulation. The results show that the switch efficiency is up to 96%; the quiescent current of this chip is only 10μA during operation, and drops below 1μA in shutdown mode; the work frequency is 1.5MHz unvaryingly. Because the main electrical characteristics can meet the specifications, the design project can be taped out.
【Key words】 DC/DC converter; current-mode; slope compensation; phase-lock loop;
- 【网络出版投稿人】 西北工业大学 【网络出版年期】2007年 06期
- 【分类号】TM44
- 【被引频次】2
- 【下载频次】362