【作者】 沈志远；

【导师】 孟桥；

【作者基本信息】 东南大学 ， 电路与系统， 2006， 硕士

【摘要】 AD转换器是现代通信、雷达、声纳以及众多消费电子产品中的关键器件。作为模拟与数字电路的接口电路的关键,高性能的模数转换器对设计系统的实现至关重要,而当今科学技术的发展对AD转换器性能,特别是速度上的要求越来越高,甚至成为决定设备性能的关键因素。本文对现今的各种高速的模数转换器的结构进行了分析,并选择了全并行结构(Flash)模数转换器作为设计课题的研究方向。论文从原理入手,系统分析了全并行结构的模数转换器的功能与特性,根据功能划分各个子模块并分别就各个子模块予以研究,在全并行模数转换理论的研究基础上着手实际电路的设计。高速模数转换集成电路设计对电路模块的失调电压、带宽等性能有很高的要求,因此本文针对各个模块的设计分别进行了具体分析和优化,设计出高速比较器和相应的纠错电路。仿真结果表明,16.6MHz输入信号在1GHz/s采样时有效位达5.9比特。积分非线性和微分非线性的最大值分别为0.4LSB和0.2LSB,1GHz/s采样时功耗约为400mW。电路采用0.18微米CMOS工艺,电源电压1.8伏。更多还原

【Abstract】 Analog-to-digital (ADC) converter is the key device of advanced communication rada acoustic susceptance and many consume eletronics .As a special interface connects with analog and digital circuits, high performance analog-to-digital converter is more and more important in whole system design. Now the development of the technology has more need of the performance of the ADC , especially the speed. It even has become the key factor of the device performance.This paper chooses Flash ADC as a object to study after analysis some high speed and resolution ADC structure nowadays. Beginning with the principle of the Flash ADC the thesis analysis its function and characteristics, then parts system into some sub-modules to further research. Because of the necessity of the high-speed ADC offset , bandwidth of the op-amp that is vital for the system design, optimization for different building blocks and digital error correction are used in this paper. The simulation indicated that it can achieves 5.9 bits for input frequency up to 16.6 MHz at 1Gsample/s. The maximum sampling speed is 1GHz. Simulated peak INL and DNL are less than 0.4LSB and 0.2LSB, respectively. This ADC consumes about 400 mW at 1Gsample/s.The chip fabricated in 0.18-μm CMOS process technology 1.8v supply.更多还原