【作者】 张玲；

【导师】 邝继顺；

【作者基本信息】 湖南大学 ， 计算机应用技术， 2005， 硕士

【摘要】 目前,集成电路测试面临两个大的问题:测试时间过长和测试功耗过高。而随着集成电路不断复杂化,测试变得更加困难。特别是对基于复用思想的SoC,虽然这种设计思想有利于减少设计成本,缩短上市时间,但测试这样复杂的系统变得异常困难。所以如何对集成电路进行高效的测试变得越来越重要。本文以缩短测试时间和减少测试功耗为目标,首先介绍了一种新的低功耗的BIST结构,并在此基础上提出了一种新的基于低功耗BIST结构的系统芯片测试方法。这种测试方法的主要思想是:将系统芯片中的多个核分成若干个大小不同的组,每个组使用一个由线性反馈移位寄存器和映射逻辑组成的低功耗内建自测试结构来进行测试,其中,线性反馈移位寄存器和映射电路是用来产生有用测试向量的,也就是说,通过映射逻辑可以将无贡献的测试向量过滤掉。组与组之间的核进行并行测试,组内各个核进行串行测试。整个结构在给定的测试功耗限制下,以测试时间为优化目标,使测试时间最短。这种测试方法的特点是:首先本方法不用外部ATE,也不依赖片上存储设备;其次本方法是用低功耗BIST来产生SoC测试时所需要的测试向量,大大减少了测试功耗、减少了测试时间;第三,本结构中,部分核共用一个BIST结构,减少了硬件开销。实验结果表明本测试方法不仅大大减少了测试时间和功耗,而且代价不大。接着本文又提出了一种新的基于状态种子的BIST策略,这种策略的主要思想是:通过统计LFSR的有用状态及其运行时间,发现LFSR的有用状态和运行时间所需要的存储空间很小,所以本策略是直接存储LFSR的状态种子及其运行时间来达到对电路的测试,实验结果表明这种方法无论在测试时间,还是在测试功耗以及所需要的存储空间上都显示出其高效性。更多还原

【Abstract】 In the mass, testing IC has two big problems: the test time is overlong and test energy is overhigh. With the IC’s architecture becoming more and more complicated, testing them becomes more and more difficult. Especially for SoC, although the SoC design style allows reuse previous designs and will lead therefore to chortor time-to-market and reduced cost, on the other hand, test SoC is big challege. So how to test IC efficiently becomes more and more important.At the target of minimize the test time and the test energy,The paper presents a new low-power BIST scheme first, then on the basis of the low-power BIST scheme, the paper proposes an new test method for the test of core-based systems. The main idea of the solution is that The cores in the systems are divided into several groups,the cores in the same group share a low-power BIST that consists of a LFSR and a mapping logic, and they are tested in sequence, the LFSR and the mapping logic is used to generating the desired vectors, and the cores not in the same group are tested concurrently, the target is to minimize the test time under the power constraint. The new test architecture has some characteristics: first, it does not use external ATE, it does not rely on memory-on-chip,neither; Second,some cores share a BIST, so it decrease the hardware overheads; third,it only generating desired vectors,so itsaves lots of test time and test energy. Experimental results show that our solution saves a significant amount of test time under the power constraint, and the hardware overhead is low.Then the paper proposes a new BIST strategy based on the state seeds. The main idea is that with the state seeds’statistic, we found that the usefull state and their test time are both very low, so we just store them on the chip memory and test the circuit. The experiments results show that the test solution is very great.更多还原